diff mbox series

efi/loongarch: Change MMU translation mode

Message ID 20231122084906.12476-1-wangyao@lemote.com
State New
Headers show
Series efi/loongarch: Change MMU translation mode | expand

Commit Message

wangyao@lemote.com Nov. 22, 2023, 8:49 a.m. UTC 
From: Wang Yao <wangyao@lemote.com>

Refer ot UEFI spec v2.10 section 2.3.8 LoongArch Platforms:

The processor is in the following execution mode during boot service:
    ...
    The memory is in physical addressing mode. LoongArch architecture
    defines two memory access mode, namely direct address translation
    mode and mapped address translation mode.

So need to change MMU translation mode before config direct mapping.

Signed-off-by: Wang Yao <wangyao@lemote.com>
---
 drivers/firmware/efi/libstub/loongarch.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/firmware/efi/libstub/loongarch.c b/drivers/firmware/efi/libstub/loongarch.c
index 807cba2693fc..4c0a84c58f5b 100644
--- a/drivers/firmware/efi/libstub/loongarch.c
+++ b/drivers/firmware/efi/libstub/loongarch.c
@@ -49,7 +49,7 @@  efi_status_t efi_boot_kernel(void *handle, efi_loaded_image_t *image,
 	struct exit_boot_struct priv;
 	unsigned long desc_size;
 	efi_status_t status;
-	u32 desc_ver;
+	u32 desc_ver, val;
 
 	status = efi_alloc_virtmap(&priv.runtime_map, &desc_size, &desc_ver);
 	if (status != EFI_SUCCESS) {
@@ -69,6 +69,12 @@  efi_status_t efi_boot_kernel(void *handle, efi_loaded_image_t *image,
 		    priv.runtime_entry_count * desc_size, desc_size,
 		    desc_ver, priv.runtime_map);
 
+	/* Change address translation mode */
+	val = csr_read32(LOONGARCH_CSR_CRMD);
+	val &= ~CSR_CRMD_DA;
+	val |= CSR_CRMD_PG;
+	csr_write32(val, LOONGARCH_CSR_CRMD);
+
 	/* Config Direct Mapping */
 	csr_write64(CSR_DMW0_INIT, LOONGARCH_CSR_DMWIN0);
 	csr_write64(CSR_DMW1_INIT, LOONGARCH_CSR_DMWIN1);