| Message ID | 20231220213615.1561528-12-Frank.Li@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,01/16] PCI: imx6: Simplify clock handling by using bulk_clk_*() function | expand |
On Wed, Dec 20, 2023 at 04:36:10PM -0500, Frank Li wrote: > From: Richard Zhu <hongxing.zhu@nxp.com> > > Add i.MX95 PCIe "fsl,imx95-pcie" compatible string. > Add "atu" and "app" to reg-names. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > > Notes: > Change from v2 to v3 > - Remove krzy's ACK tag > - Add condition check for imx95, which required more reg-names then old > platform, so need Krzy review again, > > Change from v1 to v2 > - add Krzy's ACK tag > > .../bindings/pci/fsl,imx6q-pcie-common.yaml | 1 + > .../bindings/pci/fsl,imx6q-pcie.yaml | 18 ++++++++++++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > index a284a27c5e873..1b63089ff0aee 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > @@ -207,6 +207,7 @@ allOf: > - fsl,imx6sx-pcie > - fsl,imx6q-pcie > - fsl,imx6qp-pcie > + - fsl,imx95-pcie > - fsl,imx6sx-pcie-ep > - fsl,imx6q-pcie-ep > - fsl,imx6qp-pcie-ep > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index f20d4f0e3cb6c..8633c622bd178 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -29,6 +29,7 @@ properties: > - fsl,imx8mq-pcie > - fsl,imx8mm-pcie > - fsl,imx8mp-pcie > + - fsl,imx95-pcie > > clocks: > minItems: 3 > @@ -80,6 +81,22 @@ required: > allOf: > - $ref: /schemas/pci/snps,dw-pcie.yaml# > - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# > + - if: > + properties: > + compatible: > + enum: > + - fsl,imx95-pcie > + then: > + properties: > + reg: > + minItems: 4 > + reg-names: > + items: > + - const: dbi > + - const: atu > + - const: app > + - const: config Add new entries to the end. Originally, you had dbi and config. Add ata and app on the end. > + > - if: > properties: > compatible: > @@ -101,6 +118,7 @@ allOf: > compatible: > enum: > - fsl,imx8mq-pcie > + - fsl,imx95-pcie > then: > properties: > clocks: > -- > 2.34.1 >
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index a284a27c5e873..1b63089ff0aee 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -207,6 +207,7 @@ allOf: - fsl,imx6sx-pcie - fsl,imx6q-pcie - fsl,imx6qp-pcie + - fsl,imx95-pcie - fsl,imx6sx-pcie-ep - fsl,imx6q-pcie-ep - fsl,imx6qp-pcie-ep diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index f20d4f0e3cb6c..8633c622bd178 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -29,6 +29,7 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie + - fsl,imx95-pcie clocks: minItems: 3 @@ -80,6 +81,22 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + reg: + minItems: 4 + reg-names: + items: + - const: dbi + - const: atu + - const: app + - const: config + - if: properties: compatible: @@ -101,6 +118,7 @@ allOf: compatible: enum: - fsl,imx8mq-pcie + - fsl,imx95-pcie then: properties: clocks: