@@ -716,10 +716,15 @@ static void cxl_cper_post_event(enum cxl_event_type event_type,
void cxl_cper_handle_prot_err(struct acpi_hest_generic_data *gdata)
{
+ enum cxl_event_type event_type = CXL_CPER_EVENT_PROT_ERR;
struct cxl_cper_event_info info;
if (cxl_cper_handle_prot_err_info(gdata, &info))
return;
+
+ guard(rwsem_read)(&cxl_cper_rw_sem);
+ if (cper_callback)
+ cper_callback(event_type, &info);
}
int cxl_cper_register_callback(cxl_cper_callback callback)
@@ -836,6 +836,35 @@ void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
}
EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL);
+void cxl_prot_err_trace_record(struct cxl_dev_state *cxlds,
+ struct cxl_cper_event_info *info)
+{
+ struct cper_cxl_event_sn *dev_serial_num = &info->rec.hdr.dev_serial_num;
+ u32 status, fe;
+
+ if (((u64)dev_serial_num->upper_dw << 32 |
+ dev_serial_num->lower_dw) != cxlds->serial)
+ pr_warn("The device serial number in CPER differs or isn't valid\n");
+
+ if (info->p_err.severity == CXL_AER_CORRECTABLE) {
+ status = info->p_err.cxl_ras.cor_status & ~info->p_err.cxl_ras.cor_mask;
+
+ trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
+ } else {
+ status = info->p_err.cxl_ras.uncor_status & ~info->p_err.cxl_ras.uncor_mask;
+
+ if (hweight32(status) > 1)
+ fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
+ info->p_err.cxl_ras.cap_control));
+ else
+ fe = status;
+
+ trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe,
+ info->p_err.cxl_ras.header_log);
+ }
+}
+EXPORT_SYMBOL_NS_GPL(cxl_prot_err_trace_record, CXL);
+
static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
struct cxl_dport *dport)
{
@@ -93,4 +93,7 @@ void read_cdat_data(struct cxl_port *port);
void cxl_cor_error_detected(struct pci_dev *pdev);
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state);
+struct cxl_cper_event_info;
+void cxl_prot_err_trace_record(struct cxl_dev_state *cxlds,
+ struct cxl_cper_event_info *info);
#endif /* __CXL_PCI_H__ */
@@ -995,6 +995,11 @@ static void cxl_cper_event_call(enum cxl_event_type ev_type,
if (!cxlds)
return;
+ if (ev_type == CXL_CPER_EVENT_PROT_ERR) {
+ cxl_prot_err_trace_record(cxlds, info);
+ return;
+ }
+
/* Fabricate a log type */
hdr_flags = get_unaligned_le24(info->rec.event.generic.hdr.flags);
log_type = FIELD_GET(CXL_EVENT_HDR_FLAGS_REC_SEVERITY, hdr_flags);
@@ -113,6 +113,7 @@ enum cxl_event_type {
CXL_CPER_EVENT_GEN_MEDIA,
CXL_CPER_EVENT_DRAM,
CXL_CPER_EVENT_MEM_MODULE,
+ CXL_CPER_EVENT_PROT_ERR,
};
#define CPER_CXL_DEVICE_ID_VALID BIT(0)
When PCIe AER is in FW-First, OS should process CXL Protocol errors from CPER records. These CPER records obtained from GHES module, will rely on a registered callback to be notified to the CXL subsystem in order to be processed. Call the existing cxl_cper_callback to notify the CXL subsystem on a Protocol error. The defined trace events cxl_aer_uncorrectable_error and cxl_aer_correctable_error currently trace native CXL AER errors. Reuse them to trace FW-First Protocol Errors. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- v2: Added warning for serial number check. Moved severity determination to previous patch. --- drivers/acpi/apei/ghes.c | 5 +++++ drivers/cxl/core/pci.c | 29 +++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 +++ drivers/cxl/pci.c | 5 +++++ include/linux/cxl-event.h | 1 + 5 files changed, 43 insertions(+)