diff mbox series

[v2,1/4] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets

Message ID 20240120191904.15408-2-quic_kriskura@quicinc.com
State Superseded
Headers show
Series Fix USB Interrupts on Qualcomm Platforms | expand

Commit Message

Krishna Kurapati Jan. 20, 2024, 7:19 p.m. UTC 
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.

In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.

Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.

Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
 arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
 arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
 arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
 arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
 arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
 arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
 8 files changed, 70 insertions(+), 14 deletions(-)

Comments

Bjorn Andersson Jan. 24, 2024, 9:46 p.m. UTC | #1 
On Sun, Jan 21, 2024 at 12:49:01AM +0530, Krishna Kurapati wrote:
> On several QUSB2 Targets, the hs_phy_irq mentioned is actually
> qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
> to qusb2_phy for such targets.
> 
> In actuality, the hs_phy_irq is also present in these targets, but
> kept in for debug purposes in hw test environments. This is not
> triggered by default and its functionality is mutually exclusive
> to that of qusb2_phy interrupt.
> 
> Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
> Add missing ss_phy_irq on some targets which allows for remote
> wakeup to work on a Super Speed link.
> 
> Also modify order of interrupts in accordance to bindings update.
> Since driver looks up for interrupts by name and not by index, it
> is safe to modify order of these interrupts in the DT.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
>  arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
>  arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
>  arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
>  arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
>  arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
>  arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
>  8 files changed, 70 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 5e1277fea725..ea70b57d1871 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -418,6 +418,12 @@ usb2: usb@70f8800 {
>  					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>  			assigned-clock-rates = <133330000>,
>  					       <24000000>;
> +
> +			interrupts-extended = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

interrupts-extended takes a reference to a interrupt-controller as well,
so this doesn't build.

Did you mean "interrupts" here instead? Please update these and build
test...

Regards,
Bjorn
Krishna Kurapati Jan. 26, 2024, 2:14 p.m. UTC | #2 
On 1/25/2024 3:16 AM, Bjorn Andersson wrote:
> On Sun, Jan 21, 2024 at 12:49:01AM +0530, Krishna Kurapati wrote:
>> On several QUSB2 Targets, the hs_phy_irq mentioned is actually
>> qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
>> to qusb2_phy for such targets.
>>
>> In actuality, the hs_phy_irq is also present in these targets, but
>> kept in for debug purposes in hw test environments. This is not
>> triggered by default and its functionality is mutually exclusive
>> to that of qusb2_phy interrupt.
>>
>> Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
>> Add missing ss_phy_irq on some targets which allows for remote
>> wakeup to work on a Super Speed link.
>>
>> Also modify order of interrupts in accordance to bindings update.
>> Since driver looks up for interrupts by name and not by index, it
>> is safe to modify order of these interrupts in the DT.
>>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
>>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
>>   arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
>>   arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
>>   arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
>>   arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
>>   arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
>>   arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
>>   8 files changed, 70 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> index 5e1277fea725..ea70b57d1871 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -418,6 +418,12 @@ usb2: usb@70f8800 {
>>   					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>>   			assigned-clock-rates = <133330000>,
>>   					       <24000000>;
>> +
>> +			interrupts-extended = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> 
> interrupts-extended takes a reference to a interrupt-controller as well,
> so this doesn't build.
> 
> Did you mean "interrupts" here instead? Please update these and build
> test...
> 

Hi Bjorn,

  Thanks for the catch. I was using DTC version 1.4.0.
When I moved to 1.5.0, I did see these warnings. Fixed them up and sent v3.

Thanks,
Krishna,
Krzysztof Kozlowski Jan. 26, 2024, 2:37 p.m. UTC | #3 
On 26/01/2024 15:14, Krishna Kurapati PSSNV wrote:
> 
> 
> On 1/25/2024 3:16 AM, Bjorn Andersson wrote:
>> On Sun, Jan 21, 2024 at 12:49:01AM +0530, Krishna Kurapati wrote:
>>> On several QUSB2 Targets, the hs_phy_irq mentioned is actually
>>> qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
>>> to qusb2_phy for such targets.
>>>
>>> In actuality, the hs_phy_irq is also present in these targets, but
>>> kept in for debug purposes in hw test environments. This is not
>>> triggered by default and its functionality is mutually exclusive
>>> to that of qusb2_phy interrupt.
>>>
>>> Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
>>> Add missing ss_phy_irq on some targets which allows for remote
>>> wakeup to work on a Super Speed link.
>>>
>>> Also modify order of interrupts in accordance to bindings update.
>>> Since driver looks up for interrupts by name and not by index, it
>>> is safe to modify order of these interrupts in the DT.
>>>
>>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
>>>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
>>>   arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
>>>   arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
>>>   arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
>>>   arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
>>>   arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
>>>   arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
>>>   8 files changed, 70 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>> index 5e1277fea725..ea70b57d1871 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>> @@ -418,6 +418,12 @@ usb2: usb@70f8800 {
>>>   					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
>>>   			assigned-clock-rates = <133330000>,
>>>   					       <24000000>;
>>> +
>>> +			interrupts-extended = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>>
>> interrupts-extended takes a reference to a interrupt-controller as well,
>> so this doesn't build.
>>
>> Did you mean "interrupts" here instead? Please update these and build
>> test...
>>
> 
> Hi Bjorn,
> 
>   Thanks for the catch. I was using DTC version 1.4.0.

v1.4.0? I am sorry, but what?

Isn't that like 10 years old? What systems are you using there? I am
asking, because maybe we should be rejecting DTS patches assuming they
were never tested (testing on ancient dtc counts like no testing).

> When I moved to 1.5.0, I did see these warnings. Fixed them up and sent v3.

Nope, you just moved from 10 years old to 5 years old.

Fix your systems and use the recent one. v1.6.1



Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 5e1277fea725..ea70b57d1871 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -418,6 +418,12 @@  usb2: usb@70f8800 {
 					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 			assigned-clock-rates = <133330000>,
 					       <24000000>;
+
+			interrupts-extended = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy";
+
 			resets = <&gcc GCC_USB1_BCR>;
 			status = "disabled";
 
@@ -630,6 +636,13 @@  usb3: usb@8af8800 {
 					       <133330000>,
 					       <24000000>;
 
+			interrupts-extended = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "ss_phy_irq";
+
 			resets = <&gcc GCC_USB0_BCR>;
 			status = "disabled";
 
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index cf295bed3299..c2914f827a7b 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -627,6 +627,13 @@  usb_0: usb@8af8800 {
 						<133330000>,
 						<19200000>;
 
+			interrupts-extended = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "ss_phy_irq";
+
 			power-domains = <&gcc USB0_GDSC>;
 
 			resets = <&gcc GCC_USB0_BCR>;
@@ -669,6 +676,13 @@  usb_1: usb@8cf8800 {
 						<133330000>,
 						<19200000>;
 
+			interrupts-extended = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					      <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "ss_phy_irq";
+
 			power-domains = <&gcc USB1_GDSC>;
 
 			resets = <&gcc GCC_USB1_BCR>;
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index ad2f8cf9c966..8bd1499b5c8f 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -1160,9 +1160,12 @@  usb3: usb@70f8800 {
 			#size-cells = <1>;
 			ranges;
 
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "ss_phy_irq";
 
 			clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
 				 <&gcc GCC_USB30_MASTER_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 8d41ed261adf..600720d3a8f5 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -3408,8 +3408,12 @@  usb2: usb@76f8800 {
 			#size-cells = <1>;
 			ranges;
 
-			interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq";
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq";
 
 			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 				<&gcc GCC_USB20_MASTER_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 2793cc22d381..348eee866451 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2132,9 +2132,12 @@  usb3: usb@a8f8800 {
 					  <&gcc GCC_USB30_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <120000000>;
 
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "ss_phy_irq";
 
 			power-domains = <&gcc USB_30_GDSC>;
 
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 513fe5e76b68..940901474804 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1281,9 +1281,14 @@  usb3: usb@a8f8800 {
 					  <&gcc GCC_USB30_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <120000000>;
 
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
 
 			power-domains = <&gcc USB_30_GDSC>;
 			qcom,select-utmi-as-pipe-clk;
@@ -1463,8 +1468,12 @@  usb2: usb@c2f8800 {
 					  <&gcc GCC_USB20_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <60000000>;
 
-			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq";
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq";
 
 			qcom,select-utmi-as-pipe-clk;
 
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 160e098f1075..cf8e72f06f8e 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -1586,9 +1586,14 @@  usb: usb@4ef8800 {
 					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <66666667>;
 
-			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
 
 			resets = <&gcc GCC_USB30_PRIM_BCR>;
 			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 1dd3a4056e26..00a2e0980163 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -1185,9 +1185,14 @@  usb3: usb@4ef8800 {
 					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <66666667>;
 
-			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
 
 			power-domains = <&gcc USB30_PRIM_GDSC>;
 			qcom,select-utmi-as-pipe-clk;