@@ -83,9 +83,10 @@
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b0000 0x200>;
- clock = <&clkc 4>;
+ clocks = <&clkc 4>;
+ clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart>;
};
@@ -77,9 +77,10 @@
blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
- clock = <&gcc 4>;
+ clocks = <&gcc 4>;
+ clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
};
@@ -159,31 +159,16 @@ static const struct dm_serial_ops msm_serial_ops = {
static int msm_uart_clk_init(struct udevice *dev)
{
uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 115200);
- uint clkd[2]; /* clk_id and clk_no */
- int clk_offset;
- struct udevice *clk_dev;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
- clkd, 2);
- if (ret)
- return ret;
-
- clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
- if (clk_offset < 0)
- return clk_offset;
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
- if (ret)
- return ret;
-
- clk.id = clkd[1];
- ret = clk_request(clk_dev, &clk);
- if (ret < 0)
+ ret = clk_get_by_name(dev, "core", &clk);
+ if (ret < 0) {
+ pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
return ret;
+ }
ret = clk_set_rate(&clk, clk_rate);
if (ret < 0)
return ret;
@@ -217,9 +202,8 @@ static int msm_serial_probe(struct udevice *dev)
ret = msm_uart_clk_init(dev);
if (ret)
return ret;
- pinctrl_select_state(dev, "uart");
uart_dm_init(priv);
return 0;
}
@@ -250,8 +234,9 @@ U_BOOT_DRIVER(serial_msm) = {
.of_to_plat = msm_serial_of_to_plat,
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = &msm_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_MSM