| Message ID | 20240321092529.13362-3-quic_jkona@quicinc.com |
|---|---|
| State | New |
| Headers | show
Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com
[205.220.168.131])
(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BCB256448;
Thu, 21 Mar 2024 09:26:15 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=205.220.168.131
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1711013177; cv=none;
b=J2TsFbGWPuKPbCiqTN349qo/HbTbhhW7nsPYT61jVDaxyHEab4Xb3QD9c/BAxn0qlgNHur4V18+XdP3dPbOP/DbvpdMpgMoOtC8TGMu+vPhNlFtZzRgt5Xa+wv7pO9CzvL46QAVb8EhRD0Ew58lVmtStTa+t4GtlRM7+Q9bOEXg=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1711013177; c=relaxed/simple;
bh=8XWEOdKapLVhgNj0OiRoNdThFfoU0WXVrCU4na+Fs90=;
h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:
MIME-Version:Content-Type;
b=LcYOhD2ScWagea9foa50LD+llXPLHLrnLMt8BVs8AZA0d3dIF+u2wWu2b/viY5FEVGRzM/lHiUqp78LOWCKFyyCzcwV4vPVlhHIVJ88OoQaapzGANrIzIeAX0RgXtpCBLz2CmAWn7L+MUwiPtITP8xAipHqS9uO+L/NB59DMdEQ=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com;
spf=pass smtp.mailfrom=quicinc.com;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b=magano9M; arc=none smtp.client-ip=205.220.168.131
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b="magano9M"
Received: from pps.filterd (m0279866.ppops.net [127.0.0.1])
by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id
42L7OYnl022869;
Thu, 21 Mar 2024 09:26:12 GMT
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=
from:to:cc:subject:date:message-id:in-reply-to:references
:mime-version:content-transfer-encoding:content-type; s=
qcppdkim1; bh=+xUakRsrt3VKBLKGbRWgnEX+vZzasojdWPK4rBoSEO8=; b=ma
gano9MkfNloAg2/pY0c5kmE2X0ZeJGMw/cN1Hqnb+qXGFBTfnGbz4e29fVIpWQU2
6Tyy1MUWQVQnkFEmt9yLk9hqGHs9isa2HmXtaIlJcLugYSy+QzD1gGOdCtFQ1NMm
Kgv8MOeduK4tD11JEEP887CzijL3zFiNxyPS2q/Ehycqd9vGUtDpCvM+YDCyAn7R
5bJVozsex5XXRI0w3qzJDj+bkZzR0VT3aw1enqdeeHMB+1ER8sNbzSVI84Ce8akE
PDXfz3V3phoXRZTh4wTNp6x/x769kyoiRLtPjNZ2VMR650pv/vn2tuf7kmNdlBeE
rPLVH0T7evmg9kvWVV0Q==
Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com
[129.46.96.20])
by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x0ecf0geg-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Thu, 21 Mar 2024 09:26:12 +0000 (GMT)
Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com
[10.47.209.196])
by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id
42L9QBEg018009
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Thu, 21 Mar 2024 09:26:11 GMT
Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by
nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server
(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
15.2.1118.40; Thu, 21 Mar 2024 02:26:06 -0700
From: Jagadeesh Kona <quic_jkona@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio
<konrad.dybcio@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
"Krzysztof
Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley
<conor+dt@kernel.org>
CC: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Taniya Das
<quic_tdas@quicinc.com>,
Jagadeesh Kona <quic_jkona@quicinc.com>,
"Satya
Priya Kakitapalli" <quic_skakitap@quicinc.com>,
Ajit Pandey
<quic_ajipan@quicinc.com>,
Imran Shaik <quic_imrashai@quicinc.com>
Subject: [PATCH V2 RESEND 2/6] clk: qcom: videocc-sm8550: Add support for
videocc XO clk ares
Date: Thu, 21 Mar 2024 14:55:25 +0530
Message-ID: <20240321092529.13362-3-quic_jkona@quicinc.com>
X-Mailer: git-send-email 2.43.0
In-Reply-To: <20240321092529.13362-1-quic_jkona@quicinc.com>
References: <20240321092529.13362-1-quic_jkona@quicinc.com>
Precedence: bulk
X-Mailing-List: linux-arm-msm@vger.kernel.org
List-Id: <linux-arm-msm.vger.kernel.org>
List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To
nalasex01a.na.qualcomm.com (10.47.209.196)
X-QCInternal: smtphost
X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800
signatures=585085
X-Proofpoint-GUID: 4NSJItPVZxkdt4DkJKhZhuQBRECU6lkI
X-Proofpoint-ORIG-GUID: 4NSJItPVZxkdt4DkJKhZhuQBRECU6lkI
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26
definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0
phishscore=0 clxscore=1015
priorityscore=1501 adultscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999
impostorscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0
spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1
engine=8.19.0-2403140001 definitions=main-2403210064
|
| Series |
Add support for videocc and camcc on SM8650
|
expand
|
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d2474..3a19204a9063 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = {
Add support for videocc XO clk ares for consumer drivers to be able to request for this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- drivers/clk/qcom/videocc-sm8550.c | 1 + 1 file changed, 1 insertion(+)