| Message ID | 20240416123501.12916-1-pshete@nvidia.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | gpio: tegra186: Fix tegra186_gpio_is_accessible() check | expand |
On Tue Apr 16, 2024 at 2:35 PM CEST, Prathamesh Shete wrote: > The controller has several register bits describing access control > information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it > means we have full read/write access to all the registers for given GPIO > pin. When SCR_SEC[R|W]EN is set, it means we need to further check the > accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all > the registers for given GPIO pin. > > This check was previously declaring that a GPIO pin was accessible > only if either of the following conditions were met: > > - SCR_SEC_REN + SCR_SEC_WEN both set > > or > > - SCR_SEC_REN + SCR_SEC_WEN both set and > SCR_SEC_G1R + SCR_SEC_G1W both set > > Update the check to properly handle cases where only one of > SCR_SEC_REN or SCR_SEC_WEN is set. > > Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before access.") > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > --- > drivers/gpio/gpio-tegra186.c | 22 ++++++++++++++-------- > 1 file changed, 14 insertions(+), 8 deletions(-) Acked-by: Thierry Reding <treding@nvidia.com>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> On Tue, 16 Apr 2024 18:05:01 +0530, Prathamesh Shete wrote: > The controller has several register bits describing access control > information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it > means we have full read/write access to all the registers for given GPIO > pin. When SCR_SEC[R|W]EN is set, it means we need to further check the > accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all > the registers for given GPIO pin. > > [...] Applied, thanks! [1/1] gpio: tegra186: Fix tegra186_gpio_is_accessible() check commit: 62326f7cefc21b4a7e8a1b413bf1e8bc07df1115 Best regards,
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d87dd06db40d..54c8b02eec22 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -36,12 +36,10 @@ #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) -#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN | \ - TEGRA186_GPIO_SCR_SEC_G1R | \ +#define TEGRA186_GPIO_READ_ACCESS (TEGRA186_GPIO_SCR_SEC_REN | \ + TEGRA186_GPIO_SCR_SEC_G1R) +#define TEGRA186_GPIO_WRITE_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ TEGRA186_GPIO_SCR_SEC_G1W) -#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN) /* control registers */ #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 @@ -177,10 +175,18 @@ static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned value = __raw_readl(secure + TEGRA186_GPIO_SCR); - if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0) - return true; + /* + * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the + * registers for given GPIO pin. + * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying + * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given + * GPIO pin. + */ - if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS) + if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || + (value & TEGRA186_GPIO_READ_ACCESS)) && + ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || + (value & TEGRA186_GPIO_WRITE_ACCESS))) return true; return false;
The controller has several register bits describing access control information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it means we have full read/write access to all the registers for given GPIO pin. When SCR_SEC[R|W]EN is set, it means we need to further check the accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given GPIO pin. This check was previously declaring that a GPIO pin was accessible only if either of the following conditions were met: - SCR_SEC_REN + SCR_SEC_WEN both set or - SCR_SEC_REN + SCR_SEC_WEN both set and SCR_SEC_G1R + SCR_SEC_G1W both set Update the check to properly handle cases where only one of SCR_SEC_REN or SCR_SEC_WEN is set. Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before access.") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> --- drivers/gpio/gpio-tegra186.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)