@@ -5,10 +5,8 @@
*
* Based on Linux driver
*/
-#include <clk.h>
-#include <clk-uclass.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <generic-phy.h>
@@ -16,9 +14,8 @@
#include <reset.h>
#include <asm/io.h>
#include <linux/bitops.h>
-#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
@@ -61,9 +58,8 @@
#define REFCLK_SEL_DEFAULT (0x2 << 0)
struct qcom_snps_hsphy {
void __iomem *base;
- struct clk_bulk clks;
struct reset_ctl_bulk resets;
};
/*
@@ -142,10 +138,8 @@ static int qcom_snps_hsphy_power_on(struct phy *phy)
{
struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
int ret;
- clk_enable_bulk(&priv->clks);
-
ret = reset_deassert_bulk(&priv->resets);
if (ret)
return ret;
@@ -160,9 +154,8 @@ static int qcom_snps_hsphy_power_off(struct phy *phy)
{
struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
reset_assert_bulk(&priv->resets);
- clk_disable_bulk(&priv->clks);
return 0;
}
@@ -174,21 +167,14 @@ static int qcom_snps_hsphy_phy_probe(struct udevice *dev)
priv->base = dev_read_addr_ptr(dev);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- ret = clk_get_bulk(dev, &priv->clks);
- if (ret < 0 && ret != -ENOENT) {
- printf("%s: Failed to get clocks %d\n", __func__, ret);
- return ret;
- }
-
ret = reset_get_bulk(dev, &priv->resets);
if (ret < 0) {
printf("failed to get resets, ret = %d\n", ret);
return ret;
}
- clk_enable_bulk(&priv->clks);
reset_deassert_bulk(&priv->resets);
return 0;
}
There is a clock associated with this phy, but it's always from the rpmhcc and isn't actually needed for the hardware to work. Drop all the clock handling from the driver. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> --- drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 14 -------------- 1 file changed, 14 deletions(-)