diff mbox series

[21/23] ASoC: Intel: sof-rt5682: setup pll_id only when needed

Message ID 20240426152529.38345-22-pierre-louis.bossart@linux.intel.com
State New
Headers show
Series ASoC: Intel: updates for 6.10 - part6 | expand

Commit Message

Pierre-Louis Bossart April 26, 2024, 3:25 p.m. UTC 
From: Brent Lu <brent.lu@intel.com>

The variable 'pll_id' is needed only when we use snd_soc_dai_set_pll()
to setup PLL. Move the code segment to improve some readability.

Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Brent Lu <brent.lu@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
 sound/soc/intel/boards/sof_rt5682.c | 58 ++++++++++++++---------------
 1 file changed, 29 insertions(+), 29 deletions(-)
diff mbox series

Patch

diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c
index 668b1672f570..6a79dd5271cc 100644
--- a/sound/soc/intel/boards/sof_rt5682.c
+++ b/sound/soc/intel/boards/sof_rt5682.c
@@ -320,35 +320,6 @@  static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
 		pll_in = params_rate(params) * 50;
 	}
 
-	switch (ctx->codec_type) {
-	case CODEC_RT5650:
-		pll_id = 0; /* not used in codec driver */
-		clk_id = RT5645_SCLK_S_PLL1;
-		break;
-	case CODEC_RT5682:
-		pll_id = RT5682_PLL1;
-		clk_id = RT5682_SCLK_S_PLL1;
-		break;
-	case CODEC_RT5682S:
-		/*
-		 * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1  We don't test
-		 * pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz
-		 * input, so we have no choice but to use PLL1. Besides, we will not use PLL at
-		 * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
-		 */
-		if (pll_in == 24576000) {
-			pll_id = RT5682S_PLL1;
-			clk_id = RT5682S_SCLK_S_PLL1;
-		} else {
-			pll_id = RT5682S_PLL2;
-			clk_id = RT5682S_SCLK_S_PLL2;
-		}
-		break;
-	default:
-		dev_err(rtd->dev, "invalid codec type %d\n", ctx->codec_type);
-		return -EINVAL;
-	}
-
 	pll_out = params_rate(params) * 512;
 
 	/* when MCLK is 512FS, no need to set PLL configuration additionally. */
@@ -369,6 +340,35 @@  static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
 			return -EINVAL;
 		}
 	} else {
+		switch (ctx->codec_type) {
+		case CODEC_RT5650:
+			pll_id = 0; /* not used in codec driver */
+			clk_id = RT5645_SCLK_S_PLL1;
+			break;
+		case CODEC_RT5682:
+			pll_id = RT5682_PLL1;
+			clk_id = RT5682_SCLK_S_PLL1;
+			break;
+		case CODEC_RT5682S:
+			/*
+			 * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1  We don't test
+			 * pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz
+			 * input, so we have no choice but to use PLL1. Besides, we will not use PLL at
+			 * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
+			 */
+			if (pll_in == 24576000) {
+				pll_id = RT5682S_PLL1;
+				clk_id = RT5682S_SCLK_S_PLL1;
+			} else {
+				pll_id = RT5682S_PLL2;
+				clk_id = RT5682S_SCLK_S_PLL2;
+			}
+			break;
+		default:
+			dev_err(rtd->dev, "invalid codec type %d\n", ctx->codec_type);
+			return -EINVAL;
+		}
+
 		/* Configure pll for codec */
 		ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in,
 					  pll_out);