[V5,1/6] Add PCIe pipe clock definitions for IPQ9574 SoC.

Message ID	20240512082858.1806694-2-quic_devipriy@quicinc.com
State	New
Headers	show Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E07112E71; Sun, 12 May 2024 08:29:23 +0000 (UTC) From: devi priya <quic_devipriy@quicinc.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V5 1/6] Add PCIe pipe clock definitions for IPQ9574 SoC. Date: Sun, 12 May 2024 13:58:53 +0530 Message-Id: <20240512082858.1806694-2-quic_devipriy@quicinc.com> In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com> References: <20240512082858.1806694-1-quic_devipriy@quicinc.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add PCIe support for IPQ9574 \| expand [V5,0/6] Add PCIe support for IPQ9574 [V5,1/6] Add PCIe pipe clock definitions for IPQ9574 SoC. [V5,2/6] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks [V5,3/6] dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller. [V5,4/6] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes [V5,5/6] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers [V5,6/6] PCI: qcom: Add support for IPQ9574

Message ID

20240512082858.1806694-2-quic_devipriy@quicinc.com

State

New

Headers

From: devi priya <quic_devipriy@quicinc.com>
To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
        krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org,
        konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org,
        manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Cc: quic_devipriy@quicinc.com
Subject: [PATCH V5 1/6] Add PCIe pipe clock definitions for IPQ9574 SoC.
Date: Sun, 12 May 2024 13:58:53 +0530
Message-Id: <20240512082858.1806694-2-quic_devipriy@quicinc.com>
In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com>
References: <20240512082858.1806694-1-quic_devipriy@quicinc.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add PCIe support for IPQ9574 | expand

Commit Message

Devi Priya May 12, 2024, 8:28 a.m. UTC

Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 Changes in V5:
	- No changes

 include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 08fd3a37acaa..52123c5a09fa 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -216,4 +216,8 @@ 
 #define GCC_CRYPTO_AHB_CLK				207
 #define GCC_USB0_PIPE_CLK				208
 #define GCC_USB0_SLEEP_CLK				209
+#define GCC_PCIE0_PIPE_CLK				210
+#define GCC_PCIE1_PIPE_CLK				211
+#define GCC_PCIE2_PIPE_CLK				212
+#define GCC_PCIE3_PIPE_CLK				213
 #endif

[V5,1/6] Add PCIe pipe clock definitions for IPQ9574 SoC.

Commit Message

Patch