| Message ID | 1477672015-17583-2-git-send-email-leo.duran@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
On 10/28/16 18:26, Leo Duran wrote: > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. > 2) Remove ExtractProcessorLocation() from MpInitLib library. > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran <leo.duran@amd.com> > --- > UefiCpuPkg/Include/Library/LocalApicLib.h | 18 +++ > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++++++++ > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++++++++ > UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +------------------- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +------------------ > 5 files changed, 280 insertions(+), 247 deletions(-) > mode change 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h > mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c > mode change 100644 => 100755 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c Can you please remove the file mode changes from the patch? Thank you, Laszlo > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h > old mode 100644 > new mode 100755 > index cd4e613..1d5599a > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h > @@ -21,6 +21,9 @@ > #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode. > #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode. > > +#include <PiPei.h> > +#include <Protocol/MpService.h> > + > /** > Retrieve the base address of local APIC. > > @@ -410,6 +413,21 @@ GetApicMsiValue ( > IN BOOLEAN LevelTriggered, > IN BOOLEAN AssertionLevel > ); > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical package boundaries > +with respect to the number of logical processors per package, number of cores per package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > + IN UINT32 InitialApicId, > + OUT EFI_CPU_PHYSICAL_LOCATION *Location > +); > > #endif > > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > old mode 100644 > new mode 100755 > index 8d0fb02..2995ac3 > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > @@ -941,3 +941,133 @@ GetApicMsiValue ( > } > return MsiData.Uint64; > } > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical package boundaries > +with respect to the number of logical processors per package, number of cores per package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > +IN UINT32 InitialApicId, > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > +) > +{ > + BOOLEAN TopologyLeafSupported; > + UINTN ThreadBits; > + UINTN CoreBits; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + > + // > + // Check if the processor is capable of supporting more than one logical processor. > + // > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); > + if (VersionInfoEdx.Bits.HTT == 0) { > + Location->Thread = 0; > + Location->Core = 0; > + Location->Package = 0; > + return; > + } > + > + ThreadBits = 0; > + CoreBits = 0; > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + TopologyLeafSupported = FALSE; > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + 0, > + &ExtendedTopologyEax.Uint32, > + &ExtendedTopologyEbx.Uint32, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + // > + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not > + // supported on that processor. > + // > + if (ExtendedTopologyEbx.Uint32 != 0) { > + TopologyLeafSupported = TRUE; > + > + // > + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType = ExtendedTopologyEcx.Bits.LevelType; > + ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; > + > + // > + // Software must not assume any "level type" encoding > + // value to be related to any sub-leaf index, except sub-leaf 0. > + // > + SubIndex = 1; > + do { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + SubIndex, > + &ExtendedTopologyEax.Uint32, > + NULL, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + LevelType = ExtendedTopologyEcx.Bits.LevelType; > + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); > + MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); > + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + } > + else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage = 1; > + } > + > + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); > + } > + > + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); > + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > + Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); > +} > diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > old mode 100644 > new mode 100755 > index 4c42696..60d32d2 > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > @@ -1036,3 +1036,133 @@ GetApicMsiValue ( > } > return MsiData.Uint64; > } > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical package boundaries > +with respect to the number of logical processors per package, number of cores per package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > +IN UINT32 InitialApicId, > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > +) > +{ > + BOOLEAN TopologyLeafSupported; > + UINTN ThreadBits; > + UINTN CoreBits; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + > + // > + // Check if the processor is capable of supporting more than one logical processor. > + // > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); > + if (VersionInfoEdx.Bits.HTT == 0) { > + Location->Thread = 0; > + Location->Core = 0; > + Location->Package = 0; > + return; > + } > + > + ThreadBits = 0; > + CoreBits = 0; > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + TopologyLeafSupported = FALSE; > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + 0, > + &ExtendedTopologyEax.Uint32, > + &ExtendedTopologyEbx.Uint32, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + // > + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not > + // supported on that processor. > + // > + if (ExtendedTopologyEbx.Uint32 != 0) { > + TopologyLeafSupported = TRUE; > + > + // > + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType = ExtendedTopologyEcx.Bits.LevelType; > + ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; > + > + // > + // Software must not assume any "level type" encoding > + // value to be related to any sub-leaf index, except sub-leaf 0. > + // > + SubIndex = 1; > + do { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + SubIndex, > + &ExtendedTopologyEax.Uint32, > + NULL, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + LevelType = ExtendedTopologyEcx.Bits.LevelType; > + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); > + MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); > + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + } > + else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage = 1; > + } > + > + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); > + } > + > + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); > + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > + Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); > +} > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c > old mode 100644 > new mode 100755 > index c3fe721..902e212 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( > } > > /** > - Get CPU Package/Core/Thread location information. > - > - @param[in] InitialApicId CPU APIC ID > - @param[out] Location Pointer to CPU location information > -**/ > -VOID > -ExtractProcessorLocation ( > - IN UINT32 InitialApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - BOOLEAN TopologyLeafSupported; > - UINTN ThreadBits; > - UINTN CoreBits; > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - > - // > - // Check if the processor is capable of supporting more than one logical processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); > - if (VersionInfoEdx.Bits.HTT == 0) { > - Location->Thread = 0; > - Location->Core = 0; > - Location->Package = 0; > - return; > - } > - > - ThreadBits = 0; > - CoreBits = 0; > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - TopologyLeafSupported = FALSE; > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx ( > - CPUID_EXTENDED_TOPOLOGY, > - 0, > - &ExtendedTopologyEax.Uint32, > - &ExtendedTopologyEbx.Uint32, > - &ExtendedTopologyEcx.Uint32, > - NULL > - ); > - // > - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not > - // supported on that processor. > - // > - if (ExtendedTopologyEbx.Uint32 != 0) { > - TopologyLeafSupported = TRUE; > - > - // > - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType = ExtendedTopologyEcx.Bits.LevelType; > - ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex = 1; > - do { > - AsmCpuidEx ( > - CPUID_EXTENDED_TOPOLOGY, > - SubIndex, > - &ExtendedTopologyEax.Uint32, > - NULL, > - &ExtendedTopologyEcx.Uint32, > - NULL > - ); > - LevelType = ExtendedTopologyEcx.Bits.LevelType; > - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > - break; > - } > - SubIndex++; > - } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); > - MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); > - MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage = 1; > - } > - > - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); > - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); > - Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > - Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); > -} > - > -/** > Worker function for SwitchBSP(). > > Worker function for SwitchBSP(), assigned to the AP which is intended > @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo ( > // > // Get processor location information > // > - ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location); > + GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location); > > if (HealthData != NULL) { > HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health; > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > old mode 100644 > new mode 100755 > index 40f2a17..75b5fc0 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService = { > }; > > /** > - Get Package ID/Core ID/Thread ID of a processor. > - > - APIC ID must be an initial APIC ID. > - > - The algorithm below assumes the target system has symmetry across physical package boundaries > - with respect to the number of logical processors per package, number of cores per package. > - > - @param ApicId APIC ID of the target logical processor. > - @param Location Returns the processor location information. > -**/ > -VOID > -SmmGetProcessorLocation ( > - IN UINT32 ApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - UINTN ThreadBits; > - UINTN CoreBits; > - UINT32 RegEax; > - UINT32 RegEbx; > - UINT32 RegEcx; > - UINT32 RegEdx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - BOOLEAN TopologyLeafSupported; > - > - ASSERT (Location != NULL); > - > - ThreadBits = 0; > - CoreBits = 0; > - TopologyLeafSupported = FALSE; > - > - // > - // Check if the processor is capable of supporting more than one logical processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > - ASSERT ((RegEdx & BIT28) != 0); > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL); > - // > - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not > - // supported on that processor. > - // > - if ((RegEbx & 0xffff) != 0) { > - TopologyLeafSupported = TRUE; > - > - // > - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType = (RegEcx >> 8) & 0xff; > - ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - if ((RegEbx & 0xffff) > 1 ) { > - ThreadBits = RegEax & 0x1f; > - } else { > - // > - // HT is not supported > - // > - ThreadBits = 0; > - } > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex = 1; > - do { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL); > - LevelType = (RegEcx >> 8) & 0xff; > - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits = (RegEax & 0x1f) - ThreadBits; > - break; > - } > - SubIndex++; > - } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > - MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff; > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > - MaxCoresPerPackage = (RegEax >> 26) + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage = 1; > - } > - > - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); > - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread = ApicId & ~((-1) << ThreadBits); > - Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits); > - Location->Package = (ApicId >> (ThreadBits+ CoreBits)); > -} > - > -/** > Gets processor information on the requested processor at the instant this call is made. > > @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance. > @@ -280,7 +161,7 @@ SmmAddProcessor ( > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) { > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId; > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0; > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location); > + GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location); > > *ProcessorNumber = Index; > gSmmCpuPrivate->Operation[Index] = SmmCpuAdd; > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Reply below. > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Friday, October 28, 2016 11:38 AM > To: Duran, Leo <leo.duran@amd.com>; edk2-devel@ml01.01.org > Cc: liming.gao@intel.com > Subject: Re: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to > LocalApicLib library > > On 10/28/16 18:26, Leo Duran wrote: > > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. > > 2) Remove ExtractProcessorLocation() from MpInitLib library. > > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. > > > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Leo Duran <leo.duran@amd.com> > > --- > > UefiCpuPkg/Include/Library/LocalApicLib.h | 18 +++ > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 > +++++++++++++++++++++ > > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 > +++++++++++++++++++++ > > UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +------------------- > > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +------------------ > > 5 files changed, 280 insertions(+), 247 deletions(-) mode change > > 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h > > mode change 100644 => 100755 > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > mode change 100644 => 100755 > > UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c > > mode change 100644 => 100755 > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > Can you please remove the file mode changes from the patch? [Duran, Leo] Sure thing... I'll resend it. > > Thank you, > Laszlo > > > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h > > b/UefiCpuPkg/Include/Library/LocalApicLib.h > > old mode 100644 > > new mode 100755 > > index cd4e613..1d5599a > > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h > > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h > > @@ -21,6 +21,9 @@ > > #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode. > > #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode. > > > > +#include <PiPei.h> > > +#include <Protocol/MpService.h> > > + > > /** > > Retrieve the base address of local APIC. > > > > @@ -410,6 +413,21 @@ GetApicMsiValue ( > > IN BOOLEAN LevelTriggered, > > IN BOOLEAN AssertionLevel > > ); > > + > > +/** > > +Get Package ID/Core ID/Thread ID of a processor. > > + > > +The algorithm assumes the target system has symmetry across physical > > +package boundaries with respect to the number of logical processors per > package, number of cores per package. > > + > > +@param InitialApicId Must be the initial APIC ID of the target logical > processor. > > +@param Location Returns the processor location information. > > +**/ > > +VOID > > +GetProcessorLocation( > > + IN UINT32 InitialApicId, > > + OUT EFI_CPU_PHYSICAL_LOCATION *Location ); > > > > #endif > > > > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > old mode 100644 > > new mode 100755 > > index 8d0fb02..2995ac3 > > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > @@ -941,3 +941,133 @@ GetApicMsiValue ( > > } > > return MsiData.Uint64; > > } > > + > > +/** > > +Get Package ID/Core ID/Thread ID of a processor. > > + > > +The algorithm assumes the target system has symmetry across physical > > +package boundaries with respect to the number of logical processors per > package, number of cores per package. > > + > > +@param InitialApicId Must be the initial APIC ID of the target logical > processor. > > +@param Location Returns the processor location information. > > +**/ > > +VOID > > +GetProcessorLocation( > > +IN UINT32 InitialApicId, > > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > > +) > > +{ > > + BOOLEAN TopologyLeafSupported; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + UINT32 MaxCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + > > + // > > + // Check if the processor is capable of supporting more than one > logical processor. > > + // > > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > > + if (VersionInfoEdx.Bits.HTT == 0) { > > + Location->Thread = 0; > > + Location->Core = 0; > > + Location->Package = 0; > > + return; > > + } > > + > > + ThreadBits = 0; > > + CoreBits = 0; > > + > > + // > > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // > > + > > + TopologyLeafSupported = FALSE; > > + // > > + // Get the max index of basic CPUID > > + // > > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, > NULL); > > + > > + // > > + // If the extended topology enumeration leaf is available, it > > + // is the preferred mechanism for enumerating topology. > > + // > > + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + 0, > > + &ExtendedTopologyEax.Uint32, > > + &ExtendedTopologyEbx.Uint32, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + // > > + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and > maximum input value for > > + // basic CPUID information is greater than 0BH, then > CPUID.0BH leaf is not > > + // supported on that processor. > > + // > > + if (ExtendedTopologyEbx.Uint32 != 0) { > > + TopologyLeafSupported = TRUE; > > + > > + // > > + // Sub-leaf index 0 (ECX= 0 as input) provides > enumeration parameters to extract > > + // the SMT sub-field of x2APIC ID. > > + // > > + LevelType = ExtendedTopologyEcx.Bits.LevelType; > > + ASSERT(LevelType == > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; > > + > > + // > > + // Software must not assume any "level type" > encoding > > + // value to be related to any sub-leaf index, except > sub-leaf 0. > > + // > > + SubIndex = 1; > > + do { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + SubIndex, > > + &ExtendedTopologyEax.Uint32, > > + NULL, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + LevelType = > ExtendedTopologyEcx.Bits.LevelType; > > + if (LevelType == > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > > + CoreBits = > ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > > + break; > > + } > > + SubIndex++; > > + } while (LevelType != > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + } > > + } > > + > > + if (!TopologyLeafSupported) { > > + AsmCpuid(CPUID_VERSION_INFO, NULL, > &VersionInfoEbx.Uint32, NULL, NULL); > > + MaxLogicProcessorsPerPackage = > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, > &CacheParamsEax.Uint32, NULL, NULL, NULL); > > + MaxCoresPerPackage = > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + } > > + else { > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage = 1; > > + } > > + > > + ThreadBits = > (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + > 1); > > + } > > + > > + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); > > + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > > + Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); } > > diff --git > > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > old mode 100644 > > new mode 100755 > > index 4c42696..60d32d2 > > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > @@ -1036,3 +1036,133 @@ GetApicMsiValue ( > > } > > return MsiData.Uint64; > > } > > + > > +/** > > +Get Package ID/Core ID/Thread ID of a processor. > > + > > +The algorithm assumes the target system has symmetry across physical > > +package boundaries with respect to the number of logical processors per > package, number of cores per package. > > + > > +@param InitialApicId Must be the initial APIC ID of the target logical > processor. > > +@param Location Returns the processor location information. > > +**/ > > +VOID > > +GetProcessorLocation( > > +IN UINT32 InitialApicId, > > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > > +) > > +{ > > + BOOLEAN TopologyLeafSupported; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + UINT32 MaxCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + > > + // > > + // Check if the processor is capable of supporting more than one > logical processor. > > + // > > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > > + if (VersionInfoEdx.Bits.HTT == 0) { > > + Location->Thread = 0; > > + Location->Core = 0; > > + Location->Package = 0; > > + return; > > + } > > + > > + ThreadBits = 0; > > + CoreBits = 0; > > + > > + // > > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // > > + > > + TopologyLeafSupported = FALSE; > > + // > > + // Get the max index of basic CPUID > > + // > > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, > NULL); > > + > > + // > > + // If the extended topology enumeration leaf is available, it > > + // is the preferred mechanism for enumerating topology. > > + // > > + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + 0, > > + &ExtendedTopologyEax.Uint32, > > + &ExtendedTopologyEbx.Uint32, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + // > > + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and > maximum input value for > > + // basic CPUID information is greater than 0BH, then > CPUID.0BH leaf is not > > + // supported on that processor. > > + // > > + if (ExtendedTopologyEbx.Uint32 != 0) { > > + TopologyLeafSupported = TRUE; > > + > > + // > > + // Sub-leaf index 0 (ECX= 0 as input) provides > enumeration parameters to extract > > + // the SMT sub-field of x2APIC ID. > > + // > > + LevelType = ExtendedTopologyEcx.Bits.LevelType; > > + ASSERT(LevelType == > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; > > + > > + // > > + // Software must not assume any "level type" > encoding > > + // value to be related to any sub-leaf index, except > sub-leaf 0. > > + // > > + SubIndex = 1; > > + do { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + SubIndex, > > + &ExtendedTopologyEax.Uint32, > > + NULL, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + LevelType = > ExtendedTopologyEcx.Bits.LevelType; > > + if (LevelType == > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > > + CoreBits = > ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > > + break; > > + } > > + SubIndex++; > > + } while (LevelType != > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + } > > + } > > + > > + if (!TopologyLeafSupported) { > > + AsmCpuid(CPUID_VERSION_INFO, NULL, > &VersionInfoEbx.Uint32, NULL, NULL); > > + MaxLogicProcessorsPerPackage = > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, > &CacheParamsEax.Uint32, NULL, NULL, NULL); > > + MaxCoresPerPackage = > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + } > > + else { > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage = 1; > > + } > > + > > + ThreadBits = > (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + > 1); > > + } > > + > > + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); > > + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > > + Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); } > > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > > old mode 100644 > > new mode 100755 > > index c3fe721..902e212 > > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } > > > > /** > > - Get CPU Package/Core/Thread location information. > > - > > - @param[in] InitialApicId CPU APIC ID > > - @param[out] Location Pointer to CPU location information > > -**/ > > -VOID > > -ExtractProcessorLocation ( > > - IN UINT32 InitialApicId, > > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > > - ) > > -{ > > - BOOLEAN TopologyLeafSupported; > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > - > > - // > > - // Check if the processor is capable of supporting more than one logical > processor. > > - // > > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > - if (VersionInfoEdx.Bits.HTT == 0) { > > - Location->Thread = 0; > > - Location->Core = 0; > > - Location->Package = 0; > > - return; > > - } > > - > > - ThreadBits = 0; > > - CoreBits = 0; > > - > > - // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > - // > > - > > - TopologyLeafSupported = FALSE; > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > - > > - // > > - // If the extended topology enumeration leaf is available, it > > - // is the preferred mechanism for enumerating topology. > > - // > > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx ( > > - CPUID_EXTENDED_TOPOLOGY, > > - 0, > > - &ExtendedTopologyEax.Uint32, > > - &ExtendedTopologyEbx.Uint32, > > - &ExtendedTopologyEcx.Uint32, > > - NULL > > - ); > > - // > > - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input > value for > > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is > not > > - // supported on that processor. > > - // > > - if (ExtendedTopologyEbx.Uint32 != 0) { > > - TopologyLeafSupported = TRUE; > > - > > - // > > - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters > to extract > > - // the SMT sub-field of x2APIC ID. > > - // > > - LevelType = ExtendedTopologyEcx.Bits.LevelType; > > - ASSERT (LevelType == > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > - ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; > > - > > - // > > - // Software must not assume any "level type" encoding > > - // value to be related to any sub-leaf index, except sub-leaf 0. > > - // > > - SubIndex = 1; > > - do { > > - AsmCpuidEx ( > > - CPUID_EXTENDED_TOPOLOGY, > > - SubIndex, > > - &ExtendedTopologyEax.Uint32, > > - NULL, > > - &ExtendedTopologyEcx.Uint32, > > - NULL > > - ); > > - LevelType = ExtendedTopologyEcx.Bits.LevelType; > > - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > > - CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > > - break; > > - } > > - SubIndex++; > > - } while (LevelType != > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > - } > > - } > > - > > - if (!TopologyLeafSupported) { > > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, NULL); > > - MaxLogicProcessorsPerPackage = > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > > - MaxCoresPerPackage = > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > - } else { > > - // > > - // Must be a single-core processor. > > - // > > - MaxCoresPerPackage = 1; > > - } > > - > > - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > > - } > > - > > - Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); > > - Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > > - Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -} > > - > > -/** > > Worker function for SwitchBSP(). > > > > Worker function for SwitchBSP(), assigned to the AP which is > > intended @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo ( > > // > > // Get processor location information > > // > > - ExtractProcessorLocation > > (CpuMpData->CpuData[ProcessorNumber].ApicId, > > &ProcessorInfoBuffer->Location); > > + GetProcessorLocation (CpuMpData- > >CpuData[ProcessorNumber].ApicId, > > + &ProcessorInfoBuffer->Location); > > > > if (HealthData != NULL) { > > HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health; > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > old mode 100644 > > new mode 100755 > > index 40f2a17..75b5fc0 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL > mSmmCpuService = { > > }; > > > > /** > > - Get Package ID/Core ID/Thread ID of a processor. > > - > > - APIC ID must be an initial APIC ID. > > - > > - The algorithm below assumes the target system has symmetry across > > physical package boundaries > > - with respect to the number of logical processors per package, number of > cores per package. > > - > > - @param ApicId APIC ID of the target logical processor. > > - @param Location Returns the processor location information. > > -**/ > > -VOID > > -SmmGetProcessorLocation ( > > - IN UINT32 ApicId, > > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > > - ) > > -{ > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - UINT32 RegEax; > > - UINT32 RegEbx; > > - UINT32 RegEcx; > > - UINT32 RegEdx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > - BOOLEAN TopologyLeafSupported; > > - > > - ASSERT (Location != NULL); > > - > > - ThreadBits = 0; > > - CoreBits = 0; > > - TopologyLeafSupported = FALSE; > > - > > - // > > - // Check if the processor is capable of supporting more than one logical > processor. > > - // > > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > > - ASSERT ((RegEdx & BIT28) != 0); > > - > > - // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > - // > > - > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > - > > - // > > - // If the extended topology enumeration leaf is available, it > > - // is the preferred mechanism for enumerating topology. > > - // > > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, > &RegEcx, NULL); > > - // > > - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input > value for > > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is > not > > - // supported on that processor. > > - // > > - if ((RegEbx & 0xffff) != 0) { > > - TopologyLeafSupported = TRUE; > > - > > - // > > - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters > to extract > > - // the SMT sub-field of x2APIC ID. > > - // > > - LevelType = (RegEcx >> 8) & 0xff; > > - ASSERT (LevelType == > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > - if ((RegEbx & 0xffff) > 1 ) { > > - ThreadBits = RegEax & 0x1f; > > - } else { > > - // > > - // HT is not supported > > - // > > - ThreadBits = 0; > > - } > > - > > - // > > - // Software must not assume any "level type" encoding > > - // value to be related to any sub-leaf index, except sub-leaf 0. > > - // > > - SubIndex = 1; > > - do { > > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, > NULL, &RegEcx, NULL); > > - LevelType = (RegEcx >> 8) & 0xff; > > - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > > - CoreBits = (RegEax & 0x1f) - ThreadBits; > > - break; > > - } > > - SubIndex++; > > - } while (LevelType != > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > - } > > - } > > - > > - if (!TopologyLeafSupported) { > > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > > - MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff; > > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { > > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > > - MaxCoresPerPackage = (RegEax >> 26) + 1; > > - } else { > > - // > > - // Must be a single-core processor. > > - // > > - MaxCoresPerPackage = 1; > > - } > > - > > - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > > - } > > - > > - Location->Thread = ApicId & ~((-1) << ThreadBits); > > - Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits); > > - Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -} > > - > > -/** > > Gets processor information on the requested processor at the instant this > call is made. > > > > @param[in] This A pointer to the > EFI_SMM_CPU_SERVICE_PROTOCOL instance. > > @@ -280,7 +161,7 @@ SmmAddProcessor ( > > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == > INVALID_APIC_ID) { > > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId; > > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0; > > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); > > + GetProcessorLocation ((UINT32)ProcessorId, > > + &gSmmCpuPrivate->ProcessorInfo[Index].Location); > > > > *ProcessorNumber = Index; > > gSmmCpuPrivate->Operation[Index] = SmmCpuAdd; > > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h old mode 100644 new mode 100755 index cd4e613..1d5599a --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -21,6 +21,9 @@ #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode. #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode. +#include <PiPei.h> +#include <Protocol/MpService.h> + /** Retrieve the base address of local APIC. @@ -410,6 +413,21 @@ GetApicMsiValue ( IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel ); + +/** +Get Package ID/Core ID/Thread ID of a processor. + +The algorithm assumes the target system has symmetry across physical package boundaries +with respect to the number of logical processors per package, number of cores per package. + +@param InitialApicId Must be the initial APIC ID of the target logical processor. +@param Location Returns the processor location information. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT EFI_CPU_PHYSICAL_LOCATION *Location +); #endif diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c old mode 100644 new mode 100755 index 8d0fb02..2995ac3 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -941,3 +941,133 @@ GetApicMsiValue ( } return MsiData.Uint64; } + +/** +Get Package ID/Core ID/Thread ID of a processor. + +The algorithm assumes the target system has symmetry across physical package boundaries +with respect to the number of logical processors per package, number of cores per package. + +@param InitialApicId Must be the initial APIC ID of the target logical processor. +@param Location Returns the processor location information. +**/ +VOID +GetProcessorLocation( +IN UINT32 InitialApicId, +OUT EFI_CPU_PHYSICAL_LOCATION *Location +) +{ + BOOLEAN TopologyLeafSupported; + UINTN ThreadBits; + UINTN CoreBits; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + + // + // Check if the processor is capable of supporting more than one logical processor. + // + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + if (VersionInfoEdx.Bits.HTT == 0) { + Location->Thread = 0; + Location->Core = 0; + Location->Package = 0; + return; + } + + ThreadBits = 0; + CoreBits = 0; + + // + // Assume three-level mapping of APIC ID: Package:Core:SMT. + // + + TopologyLeafSupported = FALSE; + // + // Get the max index of basic CPUID + // + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + + // + // If the extended topology enumeration leaf is available, it + // is the preferred mechanism for enumerating topology. + // + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + 0, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + // + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not + // supported on that processor. + // + if (ExtendedTopologyEbx.Uint32 != 0) { + TopologyLeafSupported = TRUE; + + // + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract + // the SMT sub-field of x2APIC ID. + // + LevelType = ExtendedTopologyEcx.Bits.LevelType; + ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; + + // + // Software must not assume any "level type" encoding + // value to be related to any sub-leaf index, except sub-leaf 0. + // + SubIndex = 1; + do { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + NULL, + &ExtendedTopologyEcx.Uint32, + NULL + ); + LevelType = ExtendedTopologyEcx.Bits.LevelType; + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; + break; + } + SubIndex++; + } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + } + } + + if (!TopologyLeafSupported) { + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; + } + else { + // + // Must be a single-core processor. + // + MaxCoresPerPackage = 1; + } + + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } + + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); +} diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c old mode 100644 new mode 100755 index 4c42696..60d32d2 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -1036,3 +1036,133 @@ GetApicMsiValue ( } return MsiData.Uint64; } + +/** +Get Package ID/Core ID/Thread ID of a processor. + +The algorithm assumes the target system has symmetry across physical package boundaries +with respect to the number of logical processors per package, number of cores per package. + +@param InitialApicId Must be the initial APIC ID of the target logical processor. +@param Location Returns the processor location information. +**/ +VOID +GetProcessorLocation( +IN UINT32 InitialApicId, +OUT EFI_CPU_PHYSICAL_LOCATION *Location +) +{ + BOOLEAN TopologyLeafSupported; + UINTN ThreadBits; + UINTN CoreBits; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + + // + // Check if the processor is capable of supporting more than one logical processor. + // + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + if (VersionInfoEdx.Bits.HTT == 0) { + Location->Thread = 0; + Location->Core = 0; + Location->Package = 0; + return; + } + + ThreadBits = 0; + CoreBits = 0; + + // + // Assume three-level mapping of APIC ID: Package:Core:SMT. + // + + TopologyLeafSupported = FALSE; + // + // Get the max index of basic CPUID + // + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + + // + // If the extended topology enumeration leaf is available, it + // is the preferred mechanism for enumerating topology. + // + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + 0, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + // + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not + // supported on that processor. + // + if (ExtendedTopologyEbx.Uint32 != 0) { + TopologyLeafSupported = TRUE; + + // + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract + // the SMT sub-field of x2APIC ID. + // + LevelType = ExtendedTopologyEcx.Bits.LevelType; + ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; + + // + // Software must not assume any "level type" encoding + // value to be related to any sub-leaf index, except sub-leaf 0. + // + SubIndex = 1; + do { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + NULL, + &ExtendedTopologyEcx.Uint32, + NULL + ); + LevelType = ExtendedTopologyEcx.Bits.LevelType; + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; + break; + } + SubIndex++; + } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + } + } + + if (!TopologyLeafSupported) { + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); + MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; + } + else { + // + // Must be a single-core processor. + // + MaxCoresPerPackage = 1; + } + + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } + + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c old mode 100644 new mode 100755 index c3fe721..902e212 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } /** - Get CPU Package/Core/Thread location information. - - @param[in] InitialApicId CPU APIC ID - @param[out] Location Pointer to CPU location information -**/ -VOID -ExtractProcessorLocation ( - IN UINT32 InitialApicId, - OUT EFI_CPU_PHYSICAL_LOCATION *Location - ) -{ - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; - - // - // Check if the processor is capable of supporting more than one logical processor. - // - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); - if (VersionInfoEdx.Bits.HTT == 0) { - Location->Thread = 0; - Location->Core = 0; - Location->Package = 0; - return; - } - - ThreadBits = 0; - CoreBits = 0; - - // - // Assume three-level mapping of APIC ID: Package:Core:SMT. - // - - TopologyLeafSupported = FALSE; - // - // Get the max index of basic CPUID - // - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); - - // - // If the extended topology enumeration leaf is available, it - // is the preferred mechanism for enumerating topology. - // - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx ( - CPUID_EXTENDED_TOPOLOGY, - 0, - &ExtendedTopologyEax.Uint32, - &ExtendedTopologyEbx.Uint32, - &ExtendedTopologyEcx.Uint32, - NULL - ); - // - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not - // supported on that processor. - // - if (ExtendedTopologyEbx.Uint32 != 0) { - TopologyLeafSupported = TRUE; - - // - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract - // the SMT sub-field of x2APIC ID. - // - LevelType = ExtendedTopologyEcx.Bits.LevelType; - ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); - ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift; - - // - // Software must not assume any "level type" encoding - // value to be related to any sub-leaf index, except sub-leaf 0. - // - SubIndex = 1; - do { - AsmCpuidEx ( - CPUID_EXTENDED_TOPOLOGY, - SubIndex, - &ExtendedTopologyEax.Uint32, - NULL, - &ExtendedTopologyEcx.Uint32, - NULL - ); - LevelType = ExtendedTopologyEcx.Bits.LevelType; - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { - CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; - break; - } - SubIndex++; - } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); - } - } - - if (!TopologyLeafSupported) { - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); - MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); - MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; - } else { - // - // Must be a single-core processor. - // - MaxCoresPerPackage = 1; - } - - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); - } - - Location->Thread = InitialApicId & ((1 << ThreadBits) - 1); - Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); - Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -} - -/** Worker function for SwitchBSP(). Worker function for SwitchBSP(), assigned to the AP which is intended @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo ( // // Get processor location information // - ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location); + GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location); if (HealthData != NULL) { HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c old mode 100644 new mode 100755 index 40f2a17..75b5fc0 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService = { }; /** - Get Package ID/Core ID/Thread ID of a processor. - - APIC ID must be an initial APIC ID. - - The algorithm below assumes the target system has symmetry across physical package boundaries - with respect to the number of logical processors per package, number of cores per package. - - @param ApicId APIC ID of the target logical processor. - @param Location Returns the processor location information. -**/ -VOID -SmmGetProcessorLocation ( - IN UINT32 ApicId, - OUT EFI_CPU_PHYSICAL_LOCATION *Location - ) -{ - UINTN ThreadBits; - UINTN CoreBits; - UINT32 RegEax; - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; - BOOLEAN TopologyLeafSupported; - - ASSERT (Location != NULL); - - ThreadBits = 0; - CoreBits = 0; - TopologyLeafSupported = FALSE; - - // - // Check if the processor is capable of supporting more than one logical processor. - // - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); - ASSERT ((RegEdx & BIT28) != 0); - - // - // Assume three-level mapping of APIC ID: Package:Core:SMT. - // - - // - // Get the max index of basic CPUID - // - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); - - // - // If the extended topology enumeration leaf is available, it - // is the preferred mechanism for enumerating topology. - // - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL); - // - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not - // supported on that processor. - // - if ((RegEbx & 0xffff) != 0) { - TopologyLeafSupported = TRUE; - - // - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract - // the SMT sub-field of x2APIC ID. - // - LevelType = (RegEcx >> 8) & 0xff; - ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); - if ((RegEbx & 0xffff) > 1 ) { - ThreadBits = RegEax & 0x1f; - } else { - // - // HT is not supported - // - ThreadBits = 0; - } - - // - // Software must not assume any "level type" encoding - // value to be related to any sub-leaf index, except sub-leaf 0. - // - SubIndex = 1; - do { - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL); - LevelType = (RegEcx >> 8) & 0xff; - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { - CoreBits = (RegEax & 0x1f) - ThreadBits; - break; - } - SubIndex++; - } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); - } - } - - if (!TopologyLeafSupported) { - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); - MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff; - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); - MaxCoresPerPackage = (RegEax >> 26) + 1; - } else { - // - // Must be a single-core processor. - // - MaxCoresPerPackage = 1; - } - - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); - } - - Location->Thread = ApicId & ~((-1) << ThreadBits); - Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits); - Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -} - -/** Gets processor information on the requested processor at the instant this call is made. @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance. @@ -280,7 +161,7 @@ SmmAddProcessor ( gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) { gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId; gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0; - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location); + GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location); *ProcessorNumber = Index; gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> --- UefiCpuPkg/Include/Library/LocalApicLib.h | 18 +++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++++++++ .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +------------------- UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +------------------ 5 files changed, 280 insertions(+), 247 deletions(-) mode change 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c mode change 100644 => 100755 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel