| Message ID | 20240815134054.44649-1-pkshih@realtek.com |
|---|---|
| State | New |
| Headers | show |
| Series | wifi: rtw89: limit the PPDU length for VHT rate to 0x40000 | expand |
Ping-Ke Shih <pkshih@realtek.com> wrote: > From: Chia-Yuan Li <leo.li@realtek.com> > > If the PPDU length for VHT rate exceeds 0x40000, calculating the PSDU > length will overflow. TMAC will determine the length to be too small and > as a result, all packets will be sent as ZLD (Zero Length Delimiter). > > Fixes: 5f7e92c59b8e ("wifi: rtw89: 8852b: set AMSDU limit to 5000") > Signed-off-by: Chia-Yuan Li <leo.li@realtek.com> > Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> 1 patch(es) applied to rtw-next branch of rtw.git, thanks. 124410976bf8 wifi: rtw89: limit the PPDU length for VHT rate to 0x40000 --- https://github.com/pkshih/rtw.git
diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index 89875f59d722..a661c176100c 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -2742,6 +2742,7 @@ bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) { + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; u32 val, reg; int ret; @@ -2780,6 +2781,12 @@ static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); } + if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { + reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); + rtw89_write32_mask(rtwdev, reg, + B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); + } + return 0; } diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 7afec48c4056..45730b0d0957 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -2506,6 +2506,10 @@ #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8) #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0) +#define R_AX_AGG_LEN_VHT_0 0xC618 +#define R_AX_AGG_LEN_VHT_0_C1 0xE618 +#define B_AX_AMPDU_MAX_LEN_VHT_MASK GENMASK(19, 0) + #define S_AX_CTS2S_TH_SEC_256B 1 #define R_AX_SIFS_SETTING 0xC624 #define R_AX_SIFS_SETTING_C1 0xE624