| Message ID | 20240925114203.2234735-1-amit.kumar-mahapatra@amd.com |
|---|---|
| State | Accepted |
| Commit | 759541d78eb8d6ac12dab7df14d4434cf5756e14 |
| Headers | show |
| Series | [v2] dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI | expand |
On Wed, 25 Sep 2024 17:12:03 +0530, Amit Kumar Mahapatra wrote: > Linear mode is only supported by the Zynq UltraScale QSPI controller, > so update the bindings to include two 'reg' properties only for the > Zynq UltraScale QSPI controller. > > Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/1] dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI commit: 759541d78eb8d6ac12dab7df14d4434cf5756e14 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index e5199b109dad..04d4d3b4916d 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -9,9 +9,6 @@ title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - Michal Simek <michal.simek@amd.com> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: enum: @@ -19,6 +16,7 @@ properties: - xlnx,zynqmp-qspi-1.0 reg: + minItems: 1 maxItems: 2 interrupts: @@ -47,6 +45,24 @@ required: unevaluatedProperties: false +allOf: + - $ref: spi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: xlnx,zynqmp-qspi-1.0 + then: + properties: + reg: + minItems: 2 + + else: + properties: + reg: + maxItems: 1 + examples: - | #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
Linear mode is only supported by the Zynq UltraScale QSPI controller, so update the bindings to include two 'reg' properties only for the Zynq UltraScale QSPI controller. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> --- BRANCH: for-next Changes in v2: - In the if block changed 'maxItems' to 'minItems'. - Retained 'reg' property definition and added 'minItems'. - Moved the allOf block down to the end of the binding. --- .../bindings/spi/spi-zynqmp-qspi.yaml | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)