diff mbox series

[V1,1/3] dt-bindings: ufs: qcom: Document ice configuration table

Message ID 20241005064307.18972-2-quic_rdwivedi@quicinc.com
State New
Headers show
Series [V1,1/3] dt-bindings: ufs: qcom: Document ice configuration table | expand

Commit Message

Ram Kumar Dwivedi Oct. 5, 2024, 6:43 a.m. UTC 
There are three algorithms supported for inline crypto engine:
Floor based, Static and Instantaneous algorithm.

Document the compatible used for the algorithm configurations
for inline crypto engine found.

Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>
---
 .../devicetree/bindings/ufs/qcom,ufs.yaml     | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Ram Kumar Dwivedi Oct. 29, 2024, 11:08 a.m. UTC | #1 
On 06-Oct-24 12:45 AM, Eric Biggers wrote:
> On Sat, Oct 05, 2024 at 12:13:05PM +0530, Ram Kumar Dwivedi wrote:
>> There are three algorithms supported for inline crypto engine:
>> Floor based, Static and Instantaneous algorithm.
> 
> No.  The algorithms supported by ICE are AES-XTS, AES-ECB, AES-CBC, etc.  So I'm
> afraid this terminology is already taken.
> 
> This new thing seems to be about how work is distributed among different
> hardware cores, so calling these "ICE schedulers" or something might make sense.
> 
> - Eric

Hi Eric,
	I have rephrased patch commit description. Used terminology as ICE allocator instead of ICE algorithm.
Thanks,
Ram.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 25a5edeea164..5ac56e164643 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -108,6 +108,11 @@  properties:
     description:
       GPIO connected to the RESET pin of the UFS memory device.
 
+  ice-config:
+    type: object
+    description:
+      ICE configuration table for Qualcom SOC
+
 required:
   - compatible
   - reg
@@ -350,5 +355,24 @@  examples:
                             <0 0>,
                             <0 0>;
             qcom,ice = <&ice>;
+
+            ice_cfg: ice-config {
+                alg1 {
+                     alg-name = "alg1";
+                     rx-alloc-percent = <60>;
+                     status = "disabled";
+                };
+
+                alg2 {
+                     alg-name = "alg2";
+                     status = "disabled";
+                };
+
+                alg3 {
+                     alg-name = "alg3";
+                     num-core = <28 28 15 13>;
+                     status = "ok";
+                };
+            };
         };
     };