| Message ID | 20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-3-074e0fb80b33@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support to scale DDR and L3 on SA8775P | expand |
On 10/26/2024 5:57 PM, Konrad Dybcio wrote: > On 17.10.2024 11:28 AM, Jagadeesh Kona wrote: >> Add LMH interrupts support to indicate if there is any >> thermal throttle. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> --- > > 'support' doesn't fit here, you're describing the interrupts, passing > them to the cpufreq node. > > Adding support for interrupts would be fitting if you e.g. added code > in the driver that would start consuming them. > > The code itself looks in line with the docs > > Konrad Sure, will update the commit text in next series. Thanks, Jagadeesh
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 47eca50b30ffa38a652706014d35ef9e833003ec..bd86bc2cb6c304aa0b4000f3226639bef57a9b9a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4005,6 +4005,10 @@ cpufreq_hw: cpufreq@18591000 { <0x0 0x18593000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate";
Add LMH interrupts support to indicate if there is any thermal throttle. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+)