| Message ID | 20241014-armv7-cacheinfo-v2-1-38ab76d2b7fa@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | ARM: implement cacheinfo support (for v7/v7m) | expand |
On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > Add functions to read the CLIDR, Cache Level ID Register. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index b9dbe1d4c8fe..b01c59076b84 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -83,6 +83,14 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } + +static inline unsigned int read_clidr(void) +{ + unsigned int val; + + asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} #else /* CONFIG_CPU_V7M */ #include <linux/io.h> #include "asm/v7m.h" @@ -96,6 +104,11 @@ static inline unsigned int read_ccsidr(void) { return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); } + +static inline unsigned int read_clidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CLIDR); +} #endif #endif
Add functions to read the CLIDR, Cache Level ID Register. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm/include/asm/cachetype.h | 13 +++++++++++++ 1 file changed, 13 insertions(+)