| Message ID | 20241018105333.4569-16-victorshihgli@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support UHS-II for GL9755 and GL9767 | expand |
Hej, On Fri, Oct 18, 2024 at 06:53:32PM +0800, Victor Shih wrote: > From: Victor Shih <victor.shih@genesyslogic.com.tw> > > Changes are: > * Disable GL9755 overcurrent interrupt when power on/off on UHS-II. > * Enable the internal clock when do reset on UHS-II mode. > * Increase timeout value before detecting UHS-II interface. > * Add vendor settings fro UHS-II mode. > * Remove sdhci_gli_enable_internal_clock functon unused clk_ctrl variable. > * Make a function sdhci_gli_wait_software_reset_done() for gl9755 reset. > * Remove unnecessary code from sdhci_gl9755_reset(). > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > Signed-off-by: Lucas Lai <lucas.lai@genesyslogic.com.tw> > --- > > drivers/mmc/host/sdhci-pci-gli.c | 235 ++++++++++++++++++++++++++++++- > 1 file changed, 234 insertions(+), 1 deletion(-) This change results in error messages / timeout about UHS2 followed by register dumps with the GL9755 integrated in Apple silicon Macbook Pros and Mac Studio systems. Non UHS-II function of controller does not seem to be affected. Apple advertises the the SDXC slot as UHS-II capable. The only quirk we've experienced with gl9755 on this platform is that 8 and 16 bit MMIO reads do not work. Workaround added in commit c064bb5c78c1b ("mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads as 32-bit reads."). If you have ideas or patches to try I'm happy to do that. If not we can look into what MacOS does. See kernel log and lspci output below Thanks, Janne [ 38.130033] kernel: sdhci: Secure Digital Host Controller Interface driver [ 38.130141] kernel: sdhci: Copyright(c) Pierre Ossman [ 38.133352] kernel: sdhci-pci 0000:02:00.0: Adding to iommu group 13 [ 38.160551] kernel: sdhci-pci 0000:02:00.0: SDHCI controller found [17a0:9755] (rev 1) [ 38.160655] kernel: sdhci-pci 0000:02:00.0: enabling device (0000 -> 0002) [ 38.160750] kernel: mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA 64-bit [ 38.274617] kernel: mmc0: not detect UHS2 interface in 100ms. [ 38.274717] kernel: mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== [ 38.274782] kernel: mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000005 [ 38.277391] kernel: mmc0: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 [ 38.277475] kernel: mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 38.280125] kernel: mmc0: sdhci: Present: 0x20070000 | Host ctl: 0x00000000 [ 38.280206] kernel: mmc0: sdhci: Power: 0x000000bf | Blk gap: 0x00000000 [ 38.284511] kernel: mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x0000032f [ 38.284592] kernel: mmc0: sdhci: Timeout: 0x00000007 | Int stat: 0x00000000 [ 38.284636] kernel: mmc0: sdhci: Int enab: 0x00ff0083 | Sig enab: 0x00ff0083 [ 38.287200] kernel: mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 38.287281] kernel: mmc0: sdhci: Caps: 0x396a3281 | Caps_1: 0x1803057f [ 38.291212] kernel: mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x000000c8 [ 38.291292] kernel: mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 [ 38.291335] kernel: mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 [ 38.293513] kernel: mmc0: sdhci: Host ctl2: 0x00009107 [ 38.293604] kernel: mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 [ 38.297842] kernel: mmc0: sdhci_uhs2: ==================== UHS2 ================== [ 38.297923] kernel: mmc0: sdhci_uhs2: Blk Size: 0x00000000 | Blk Cnt: 0x00000000 [ 38.297968] kernel: mmc0: sdhci_uhs2: Cmd: 0x00000000 | Trn mode: 0x00000000 [ 38.300773] kernel: mmc0: sdhci_uhs2: Int Stat: 0x00000000 | Dev Sel : 0x00000000 [ 38.300853] kernel: mmc0: sdhci_uhs2: Dev Int Code: 0x00000000 [ 38.304739] kernel: mmc0: sdhci_uhs2: Reset: 0x00000000 | Timer: 0x000000a7 [ 38.304811] kernel: mmc0: sdhci_uhs2: ErrInt: 0x00000000 | ErrIntEn: 0x00030000 [ 38.304856] kernel: mmc0: sdhci_uhs2: ErrSigEn: 0x00030000 [ 38.307110] kernel: mmc0: sdhci: ============================================ [ 38.307201] kernel: mmc0: cannot detect UHS2 interface. [ 38.310110] kernel: mmc0: failed to initial phy for UHS-II! [ 38.424645] kernel: mmc0: not detect UHS2 interface in 100ms. [ 38.424731] kernel: mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== [ 38.424758] kernel: mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000005 [ 38.424782] kernel: mmc0: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 [ 38.424840] kernel: mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 38.427603] kernel: mmc0: sdhci: Present: 0x20070000 | Host ctl: 0x00000000 [ 38.427659] kernel: mmc0: sdhci: Power: 0x000000bf | Blk gap: 0x00000000 [ 38.430579] kernel: mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x0000032f [ 38.430626] kernel: mmc0: sdhci: Timeout: 0x00000007 | Int stat: 0x00000000 [ 38.433504] kernel: mmc0: sdhci: Int enab: 0x00ff0083 | Sig enab: 0x00ff0083 [ 38.433550] kernel: mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 38.437596] kernel: mmc0: sdhci: Caps: 0x396a3281 | Caps_1: 0x1803057f [ 38.437641] kernel: mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x000000c8 [ 38.437677] kernel: mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 [ 38.440318] kernel: mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 [ 38.440345] kernel: mmc0: sdhci: Host ctl2: 0x00009107 [ 38.444119] kernel: mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 [ 38.444161] kernel: mmc0: sdhci_uhs2: ==================== UHS2 ================== [ 38.444184] kernel: mmc0: sdhci_uhs2: Blk Size: 0x00000000 | Blk Cnt: 0x00000000 [ 38.446918] kernel: mmc0: sdhci_uhs2: Cmd: 0x00000000 | Trn mode: 0x00000000 [ 38.446958] kernel: mmc0: sdhci_uhs2: Int Stat: 0x00000000 | Dev Sel : 0x00000000 [ 38.450833] kernel: mmc0: sdhci_uhs2: Dev Int Code: 0x00000000 [ 38.450874] kernel: mmc0: sdhci_uhs2: Reset: 0x00000000 | Timer: 0x000000a7 [ 38.450907] kernel: mmc0: sdhci_uhs2: ErrInt: 0x00000000 | ErrIntEn: 0x00030000 [ 38.454625] kernel: mmc0: sdhci_uhs2: ErrSigEn: 0x00030000 [ 38.454665] kernel: mmc0: sdhci: ============================================ [ 38.454699] kernel: mmc0: cannot detect UHS2 interface. [ 38.456705] kernel: mmc0: failed to initial phy for UHS-II! `lspci -vvvnn -d 17a0:9755` output: 02:00.0 SD Host controller [0805]: Genesys Logic, Inc GL9755 SD Host Controller [17a0:9755] (rev 01) (prog-if 01) Subsystem: Genesys Logic, Inc GL9755 SD Host Controller [17a0:9755] Device tree node: /sys/firmware/devicetree/base/soc@200000000/pcie@590000000/pci@1,0/mmc@0,0 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 168 IOMMU group: 13 Region 0: Memory at 5c1e00000 (32-bit, non-prefetchable) [size=4K] Capabilities: [80] Express (v2) Endpoint, IntMsgNum 0 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0W TEE-IO- DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- LnkCap: Port #85, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 unlimited ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1 TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+ 10BitTagComp- 10BitTagReq- OBFF Via message/WAKE#, ExtFmt- EETLPPrefix- EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- FRS- TPHComp- ExtTPHComp- AtomicOpsCap: 32bit- 64bit- 128bitCAS- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- AtomicOpsCtl: ReqEn- IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq- 10BitTagReq- OBFF Disabled, EETLPPrefixBlk- LnkCap2: Supported Link Speeds: 2.5-5GT/s, Crosslink- Retimer- 2Retimers- DRS- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1- EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest- Retimer- 2Retimers- CrosslinkRes: unsupported Capabilities: [e0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fffff000 Data: 0018 Capabilities: [f8] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME+ Capabilities: [100 v1] Vendor Specific Information: ID=17a0 Rev=1 Len=008 <?> Capabilities: [108 v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Capabilities: [110 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ PortCommonModeRestoreTime=255us PortTPowerOnTime=3100us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- T_CommonMode=0us LTR1.2_Threshold=3375104ns L1SubCtl2: T_PwrOn=3100us Capabilities: [200 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrIntErr- HeaderOF- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout+ AdvNonFatalErr+ CorrIntErr- HeaderOF- AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- HeaderLog: 00000000 00000000 00000000 00000000 Kernel driver in use: sdhci-pci Kernel modules: sdhci_pci
On 5/03/25 02:56, Ben Chuang wrote: > Hi Janne, > > On Thu, Feb 20, 2025 at 5:32 AM Janne Grunau <j@jannau.net> wrote: >> >> Hej, >> >> On Fri, Oct 18, 2024 at 06:53:32PM +0800, Victor Shih wrote: >>> From: Victor Shih <victor.shih@genesyslogic.com.tw> >>> >>> Changes are: >>> * Disable GL9755 overcurrent interrupt when power on/off on UHS-II. >>> * Enable the internal clock when do reset on UHS-II mode. >>> * Increase timeout value before detecting UHS-II interface. >>> * Add vendor settings fro UHS-II mode. >>> * Remove sdhci_gli_enable_internal_clock functon unused clk_ctrl variable. >>> * Make a function sdhci_gli_wait_software_reset_done() for gl9755 reset. >>> * Remove unnecessary code from sdhci_gl9755_reset(). >>> >>> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> >>> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> >>> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> >>> Signed-off-by: Lucas Lai <lucas.lai@genesyslogic.com.tw> >>> --- >>> >>> drivers/mmc/host/sdhci-pci-gli.c | 235 ++++++++++++++++++++++++++++++- >>> 1 file changed, 234 insertions(+), 1 deletion(-) >> >> This change results in error messages / timeout about UHS2 followed by >> register dumps with the GL9755 integrated in Apple silicon Macbook Pros >> and Mac Studio systems. Non UHS-II function of controller does not seem >> to be affected. Apple advertises the the SDXC slot as UHS-II capable. >> >> The only quirk we've experienced with gl9755 on this platform is that 8 >> and 16 bit MMIO reads do not work. Workaround added in commit >> c064bb5c78c1b ("mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads >> as 32-bit reads."). >> >> If you have ideas or patches to try I'm happy to do that. If not we can >> look into what MacOS does. >> >> See kernel log and lspci output below >> >> Thanks, >> Janne >> >> [ 38.130033] kernel: sdhci: Secure Digital Host Controller Interface driver >> [ 38.130141] kernel: sdhci: Copyright(c) Pierre Ossman >> [ 38.133352] kernel: sdhci-pci 0000:02:00.0: Adding to iommu group 13 >> [ 38.160551] kernel: sdhci-pci 0000:02:00.0: SDHCI controller found [17a0:9755] (rev 1) >> [ 38.160655] kernel: sdhci-pci 0000:02:00.0: enabling device (0000 -> 0002) >> [ 38.160750] kernel: mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA 64-bit >> [ 38.274617] kernel: mmc0: not detect UHS2 interface in 100ms. >> [ 38.274717] kernel: mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== >> [ 38.274782] kernel: mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000005 >> [ 38.277391] kernel: mmc0: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 >> [ 38.277475] kernel: mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 >> [ 38.280125] kernel: mmc0: sdhci: Present: 0x20070000 | Host ctl: 0x00000000 >> [ 38.280206] kernel: mmc0: sdhci: Power: 0x000000bf | Blk gap: 0x00000000 >> [ 38.284511] kernel: mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x0000032f >> [ 38.284592] kernel: mmc0: sdhci: Timeout: 0x00000007 | Int stat: 0x00000000 >> [ 38.284636] kernel: mmc0: sdhci: Int enab: 0x00ff0083 | Sig enab: 0x00ff0083 >> [ 38.287200] kernel: mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 >> [ 38.287281] kernel: mmc0: sdhci: Caps: 0x396a3281 | Caps_1: 0x1803057f >> [ 38.291212] kernel: mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x000000c8 >> [ 38.291292] kernel: mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 >> [ 38.291335] kernel: mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 >> [ 38.293513] kernel: mmc0: sdhci: Host ctl2: 0x00009107 >> [ 38.293604] kernel: mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 >> [ 38.297842] kernel: mmc0: sdhci_uhs2: ==================== UHS2 ================== >> [ 38.297923] kernel: mmc0: sdhci_uhs2: Blk Size: 0x00000000 | Blk Cnt: 0x00000000 >> [ 38.297968] kernel: mmc0: sdhci_uhs2: Cmd: 0x00000000 | Trn mode: 0x00000000 >> [ 38.300773] kernel: mmc0: sdhci_uhs2: Int Stat: 0x00000000 | Dev Sel : 0x00000000 >> [ 38.300853] kernel: mmc0: sdhci_uhs2: Dev Int Code: 0x00000000 >> [ 38.304739] kernel: mmc0: sdhci_uhs2: Reset: 0x00000000 | Timer: 0x000000a7 >> [ 38.304811] kernel: mmc0: sdhci_uhs2: ErrInt: 0x00000000 | ErrIntEn: 0x00030000 >> [ 38.304856] kernel: mmc0: sdhci_uhs2: ErrSigEn: 0x00030000 >> [ 38.307110] kernel: mmc0: sdhci: ============================================ >> [ 38.307201] kernel: mmc0: cannot detect UHS2 interface. >> [ 38.310110] kernel: mmc0: failed to initial phy for UHS-II! >> [ 38.424645] kernel: mmc0: not detect UHS2 interface in 100ms. >> [ 38.424731] kernel: mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== >> [ 38.424758] kernel: mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000005 >> [ 38.424782] kernel: mmc0: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 >> [ 38.424840] kernel: mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 >> [ 38.427603] kernel: mmc0: sdhci: Present: 0x20070000 | Host ctl: 0x00000000 >> [ 38.427659] kernel: mmc0: sdhci: Power: 0x000000bf | Blk gap: 0x00000000 >> [ 38.430579] kernel: mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x0000032f >> [ 38.430626] kernel: mmc0: sdhci: Timeout: 0x00000007 | Int stat: 0x00000000 >> [ 38.433504] kernel: mmc0: sdhci: Int enab: 0x00ff0083 | Sig enab: 0x00ff0083 >> [ 38.433550] kernel: mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 >> [ 38.437596] kernel: mmc0: sdhci: Caps: 0x396a3281 | Caps_1: 0x1803057f >> [ 38.437641] kernel: mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x000000c8 >> [ 38.437677] kernel: mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 >> [ 38.440318] kernel: mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 >> [ 38.440345] kernel: mmc0: sdhci: Host ctl2: 0x00009107 >> [ 38.444119] kernel: mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 >> [ 38.444161] kernel: mmc0: sdhci_uhs2: ==================== UHS2 ================== >> [ 38.444184] kernel: mmc0: sdhci_uhs2: Blk Size: 0x00000000 | Blk Cnt: 0x00000000 >> [ 38.446918] kernel: mmc0: sdhci_uhs2: Cmd: 0x00000000 | Trn mode: 0x00000000 >> [ 38.446958] kernel: mmc0: sdhci_uhs2: Int Stat: 0x00000000 | Dev Sel : 0x00000000 >> [ 38.450833] kernel: mmc0: sdhci_uhs2: Dev Int Code: 0x00000000 >> [ 38.450874] kernel: mmc0: sdhci_uhs2: Reset: 0x00000000 | Timer: 0x000000a7 >> [ 38.450907] kernel: mmc0: sdhci_uhs2: ErrInt: 0x00000000 | ErrIntEn: 0x00030000 >> [ 38.454625] kernel: mmc0: sdhci_uhs2: ErrSigEn: 0x00030000 >> [ 38.454665] kernel: mmc0: sdhci: ============================================ >> [ 38.454699] kernel: mmc0: cannot detect UHS2 interface. >> [ 38.456705] kernel: mmc0: failed to initial phy for UHS-II! >> > > On which UHS-II card does this message appear? Please share the card > information. > If it is a UHS-I card, this message is normal. If it is normal, we should not be producing error messages and register dumps. Please change all these messages to be debug only. The register dump can go behind DYNAMIC_DEBUG_BRANCH().
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 0f81586a19df..708138eecaa7 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -18,6 +18,7 @@ #include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" +#include "sdhci-uhs2.h" /* Genesys Logic extra registers */ #define SDHCI_GLI_9750_WT 0x800 @@ -139,9 +140,36 @@ #define PCI_GLI_9755_PLLSSC 0x68 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) +#define PCI_GLI_9755_PLLSSC_RTL BIT(24) +#define GLI_9755_PLLSSC_RTL_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) +#define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) +#define GLI_9755_PLLSSC_RECV_VALUE 0x0 +#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) +#define GLI_9755_PLLSSC_TRAN_VALUE 0x3 + +#define PCI_GLI_9755_UHS2_PLL 0x6C +#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) +#define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 +#define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) +#define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 +#define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) +#define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 #define PCI_GLI_9755_SerDes 0x70 +#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) +#define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 +#define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) +#define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 +#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) +#define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB +#define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 #define PCI_GLI_9755_SCP_DIS BIT(19) +#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) +#define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC +#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) +#define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) @@ -779,6 +807,203 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) gl9755_wt_off(pdev); } +static void gl9755_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct pci_dev *pdev = slot->chip->pdev; + u32 serdes; + u32 pllssc; + u32 uhs2_pll; + + gl9755_wt_on(pdev); + + pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, + GLI_9755_UHS2_SERDES_TRAN_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, + GLI_9755_UHS2_SERDES_RECV_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, + GLI_9755_UHS2_SERDES_INTR_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, + GLI_9755_UHS2_SERDES_ZC1_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_DEFAULT); + pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); + + pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, + GLI_9755_UHS2_PLL_SSC_VALUE); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, + GLI_9755_UHS2_PLL_DELAY_VALUE); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, + GLI_9755_UHS2_PLL_PDRST_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); + + pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); + pllssc &= ~PCI_GLI_9755_PLLSSC_RTL; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, + GLI_9755_PLLSSC_RTL_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, + GLI_9755_PLLSSC_TRANS_PASS_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_RECV; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, + GLI_9755_PLLSSC_RECV_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, + GLI_9755_PLLSSC_TRAN_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); + + gl9755_wt_off(pdev); +} + +static void sdhci_gli_pre_detect_init(struct sdhci_host *host) +{ + /* Need more time on UHS2 detect flow */ + sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); +} + +static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable) +{ + u32 mask; + + mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); + if (enable) + mask |= SDHCI_INT_BUS_POWER; + else + mask &= ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); + + mask = sdhci_readl(host, SDHCI_INT_ENABLE); + if (enable) + mask |= SDHCI_INT_BUS_POWER; + else + mask &= ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_INT_ENABLE); +} + +static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr = 0; + + if (mode != MMC_POWER_OFF) { + pwr = sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); + pwr |= SDHCI_VDD2_POWER_180; + } + + if (host->pwr == pwr) + return; + + host->pwr = pwr; + + if (pwr == 0) { + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + } else { + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); + + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_gli_overcurrent_event_enable(host, true); + } +} + +static bool sdhci_wait_clock_stable(struct sdhci_host *host) +{ + u16 clk = 0; + + if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), + 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return false; + } + return true; +} + +static void sdhci_gli_enable_internal_clock(struct sdhci_host *host) +{ + u16 ctrl2; + + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); + + if (!((ctrl2 & SDHCI_CTRL_V4_MODE) && + (ctrl2 & SDHCI_CTRL_UHS2_ENABLE))) { + sdhci_wait_clock_stable(host); + sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); + } +} + +static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 mask) +{ + u8 rst; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), + 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { + pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); + sdhci_dumpregs(host); + /* manual clear */ + sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); + return -ETIMEDOUT; + } + + return 0; +} + +static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) +{ + /* do this on UHS2 mode */ + if (host->mmc->uhs2_sd_tran) { + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + sdhci_uhs2_clear_set_irqs(host, + SDHCI_INT_ALL_MASK, + SDHCI_UHS2_INT_ERROR_MASK); + } +} + +static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) +{ + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) + sdhci_gli_enable_internal_clock(host); + + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + + /* reset sd-tran on UHS2 mode if need to reset cmd/data */ + if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) + sdhci_gli_uhs2_reset_sd_tran(host); + + if (mask & SDHCI_RESET_ALL) + host->clock = 0; + + sdhci_gli_wait_software_reset_done(host, mask); +} + static inline void gl9767_vhs_read(struct pci_dev *pdev) { u32 vhs_enable; @@ -1086,6 +1311,7 @@ static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) gli_pcie_enable_msi(slot); slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; sdhci_enable_v4_mode(host); + gl9755_vendor_init(host); return 0; } @@ -1524,17 +1750,24 @@ static const struct sdhci_ops sdhci_gl9755_ops = { .read_w = sdhci_gli_readw, .read_b = sdhci_gli_readb, .set_clock = sdhci_gl9755_set_clock, + .set_power = gl9755_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, + .reset = sdhci_gl9755_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .voltage_switch = sdhci_gli_voltage_switch, + .dump_uhs2_regs = sdhci_uhs2_dump_regs, + .set_timeout = sdhci_uhs2_set_timeout, + .irq = sdhci_uhs2_irq, + .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, }; const struct sdhci_pci_fixes sdhci_gl9755 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9755, + .add_host = sdhci_pci_uhs2_add_host, + .remove_host = sdhci_pci_uhs2_remove_host, .ops = &sdhci_gl9755_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume,