| Message ID | 20241017190809.16942-1-ansuelsmth@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] cpufreq: airoha: Add EN7581 Cpufreq SMC driver | expand |
On Thu, Oct 17, 2024 at 09:07:49PM +0200, Christian Marangi wrote: > Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU > frequency scaling with SMC APIs. > > All CPU share the same frequency and can't be controlled independently. > Current shared CPU frequency is returned by the related SMC command. > > Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq > driver is needed with OPP v2 nodes declared in DTS. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Sorry to ask but any news with this?
On 17-10-24, 21:07, Christian Marangi wrote: > Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU > frequency scaling with SMC APIs. > > All CPU share the same frequency and can't be controlled independently. > Current shared CPU frequency is returned by the related SMC command. > > Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq > driver is needed with OPP v2 nodes declared in DTS. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > Changes v2: > - Fix kernel bot error with missing slab.h and bitfield.h header > - Limit COMPILE_TEST to ARM64 due to smcc 1.2 Hi, Sorry for delay at my side to review this driver. Now that I looked at it, I don't see a lot of special stuff happening in the driver. There are many other platforms with similar situation. What we have done for all them, which rely on OPPs coming from DT, is to add a clk for the CPUs and do all this magically smcc stuff from clk_get_rate() and clk_set_rate(). Once that is done, you should be able to reuse the cpufreq-dt driver as is. So a CPU clk is the only missing thing in your case I guess.
On Tue, Nov 19, 2024 at 12:50:54PM +0530, Viresh Kumar wrote: > On 17-10-24, 21:07, Christian Marangi wrote: > > Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU > > frequency scaling with SMC APIs. > > > > All CPU share the same frequency and can't be controlled independently. > > Current shared CPU frequency is returned by the related SMC command. > > > > Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq > > driver is needed with OPP v2 nodes declared in DTS. > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > --- > > Changes v2: > > - Fix kernel bot error with missing slab.h and bitfield.h header > > - Limit COMPILE_TEST to ARM64 due to smcc 1.2 > > Hi, > > Sorry for delay at my side to review this driver. > > Now that I looked at it, I don't see a lot of special stuff happening in the > driver. There are many other platforms with similar situation. What we have done > for all them, which rely on OPPs coming from DT, is to add a clk for the CPUs > and do all this magically smcc stuff from clk_get_rate() and clk_set_rate(). > Once that is done, you should be able to reuse the cpufreq-dt driver as is. > > So a CPU clk is the only missing thing in your case I guess. > Hi Viresh, thanks a lot for the follow-up. I will see what I can do, 2 main problem I see is that, contrary to other driver, for this Airoha SoC, there are no parents or no clock to enable... It's really just entirely handled by ATF and smccc call. And also the SMCCC requires an index and not the clock itself. This was handy for a cpufreq driver as it passed the OPP index, problematic for a clock driver as set_rate pass the clock. So I guess I will have to define the OPP phandle also in the clock node struct. (and map it?) The main problem in doing that is the performance hit on having to cycle every time the OPPs to find the correct index... (yes they really implemented this thing with the ATF specifically with the cpufreq scenario in mind) Wonder if you have any hint on any of this.
On 19-11-24, 10:04, Christian Marangi wrote: > On Tue, Nov 19, 2024 at 12:50:54PM +0530, Viresh Kumar wrote: > > On 17-10-24, 21:07, Christian Marangi wrote: > > > Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU > > > frequency scaling with SMC APIs. > > > > > > All CPU share the same frequency and can't be controlled independently. > > > Current shared CPU frequency is returned by the related SMC command. > > > > > > Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq > > > driver is needed with OPP v2 nodes declared in DTS. > > > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > > --- > > > Changes v2: > > > - Fix kernel bot error with missing slab.h and bitfield.h header > > > - Limit COMPILE_TEST to ARM64 due to smcc 1.2 > > > > Hi, > > > > Sorry for delay at my side to review this driver. > > > > Now that I looked at it, I don't see a lot of special stuff happening in the > > driver. There are many other platforms with similar situation. What we have done > > for all them, which rely on OPPs coming from DT, is to add a clk for the CPUs > > and do all this magically smcc stuff from clk_get_rate() and clk_set_rate(). > > Once that is done, you should be able to reuse the cpufreq-dt driver as is. > > > > So a CPU clk is the only missing thing in your case I guess. > > > > Hi Viresh, > > thanks a lot for the follow-up. I will see what I can do, 2 main problem > I see is that, contrary to other driver, for this Airoha SoC, there are > no parents or no clock to enable... It's really just entirely handled by > ATF and smccc call. > > And also the SMCCC requires an index and not the clock itself. This was > handy for a cpufreq driver as it passed the OPP index Right, but the OPP table for the CPU must contain frequencies too, isn't it ? So you already have index to frequency conversion available ? Can't you just add a clk driver for the CPU, which uses OPP core to parse the OPP table of the CPU and set a clk-index table in the clk driver ? So once the clk driver gets a request for a particular frequency, it just finds the respective index and sets it ? > problematic for a > clock driver as set_rate pass the clock. So I guess I will have to > define the OPP phandle also in the clock node struct. (and map it?) I am not suggesting a clk in DT, but just in code, added by a cpufreq driver for your platform, which at the end creates cpufreq-dt device. There are many which are creating the device on the fly, like tegra20-cpufreq.c. > The main problem in doing that is the performance hit on having to cycle > every time the OPPs to find the correct index... I think it would be traversing an array in the clk driver eventually and that won't be that bad ? > (yes they really implemented this thing with the ATF specifically with > the cpufreq scenario in mind)
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 5f7e13e60c80..338fc54276f2 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -15,6 +15,14 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM To compile this driver as a module, choose M here: the module will be called sun50i-cpufreq-nvmem. +config ARM_AIROHA_SOC_CPUFREQ + tristate "Airoha EN7581 SoC CPUFreq support" + depends on ARCH_AIROHA || (COMPILE_TEST && ARM64) + select PM_OPP + default ARCH_AIROHA + help + This adds the CPUFreq driver for Airoha EN7581 SoCs. + config ARM_APPLE_SOC_CPUFREQ tristate "Apple Silicon SoC CPUFreq support" depends on ARCH_APPLE || (COMPILE_TEST && 64BIT) diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 0f184031dd12..8e5a37a95d36 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY) += amd_freq_sensitivity.o ################################################################################## # ARM SoC drivers +obj-$(CONFIG_ARM_AIROHA_SOC_CPUFREQ) += airoha-cpufreq.o obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ) += apple-soc-cpufreq.o obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ) += armada-8k-cpufreq.o diff --git a/drivers/cpufreq/airoha-cpufreq.c b/drivers/cpufreq/airoha-cpufreq.c new file mode 100644 index 000000000000..f8bbc142837c --- /dev/null +++ b/drivers/cpufreq/airoha-cpufreq.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <linux/bitfield.h> +#include <linux/cpufreq.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/arm-smccc.h> + +#define AIROHA_SIP_AVS_HANDLE 0x82000301 +#define AIROHA_AVS_OP_BASE 0xddddddd0 +#define AIROHA_AVS_OP_MASK GENMASK(1, 0) +#define AIROHA_AVS_OP_FREQ_DYN_ADJ (AIROHA_AVS_OP_BASE | \ + FIELD_PREP(AIROHA_AVS_OP_MASK, 0x1)) +#define AIROHA_AVS_OP_GET_FREQ (AIROHA_AVS_OP_BASE | \ + FIELD_PREP(AIROHA_AVS_OP_MASK, 0x2)) + +struct airoha_cpufreq_priv { + struct list_head list; + + cpumask_var_t cpus; + struct device *cpu_dev; + struct cpufreq_frequency_table *freq_table; +}; + +static LIST_HEAD(priv_list); + +static unsigned int airoha_cpufreq_get(unsigned int cpu) +{ + const struct arm_smccc_1_2_regs args = { + .a0 = AIROHA_SIP_AVS_HANDLE, + .a1 = AIROHA_AVS_OP_GET_FREQ, + }; + struct arm_smccc_1_2_regs res; + + arm_smccc_1_2_smc(&args, &res); + + return (int)(res.a0 * 1000); +} + +static int airoha_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) +{ + const struct arm_smccc_1_2_regs args = { + .a0 = AIROHA_SIP_AVS_HANDLE, + .a1 = AIROHA_AVS_OP_FREQ_DYN_ADJ, + .a3 = index, + }; + struct arm_smccc_1_2_regs res; + + arm_smccc_1_2_smc(&args, &res); + + /* SMC signal correct apply by unsetting BIT 0 */ + return res.a0 & BIT(0) ? -EINVAL : 0; +} + +static struct airoha_cpufreq_priv *airoha_cpufreq_find_data(int cpu) +{ + struct airoha_cpufreq_priv *priv; + + list_for_each_entry(priv, &priv_list, list) { + if (cpumask_test_cpu(cpu, priv->cpus)) + return priv; + } + + return NULL; +} + +static int airoha_cpufreq_init(struct cpufreq_policy *policy) +{ + struct airoha_cpufreq_priv *priv; + + priv = airoha_cpufreq_find_data(policy->cpu); + if (!priv) + return -ENODEV; + + cpumask_copy(policy->cpus, priv->cpus); + policy->driver_data = priv; + policy->freq_table = priv->freq_table; + + return 0; +} + +static struct cpufreq_driver airoha_cpufreq_driver = { + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | + CPUFREQ_IS_COOLING_DEV, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = airoha_cpufreq_set_target, + .get = airoha_cpufreq_get, + .init = airoha_cpufreq_init, + .attr = cpufreq_generic_attr, + .name = "airoha-cpufreq", +}; + +static int airoha_cpufreq_driver_init_cpu(int cpu) +{ + struct airoha_cpufreq_priv *priv; + struct device *cpu_dev; + int ret; + + cpu_dev = get_cpu_device(cpu); + if (!cpu_dev) + return -EPROBE_DEFER; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + if (!zalloc_cpumask_var(&priv->cpus, GFP_KERNEL)) + return -ENOMEM; + + cpumask_set_cpu(cpu, priv->cpus); + priv->cpu_dev = cpu_dev; + + ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, priv->cpus); + if (ret) + goto err; + + ret = dev_pm_opp_of_cpumask_add_table(priv->cpus); + if (ret) + goto err; + + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &priv->freq_table); + if (ret) + goto err; + + list_add(&priv->list, &priv_list); + + return 0; + +err: + dev_pm_opp_of_cpumask_remove_table(priv->cpus); + free_cpumask_var(priv->cpus); + + return ret; +} + +static void airoha_cpufreq_release(void) +{ + struct airoha_cpufreq_priv *priv, *tmp; + + list_for_each_entry_safe(priv, tmp, &priv_list, list) { + dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &priv->freq_table); + dev_pm_opp_of_cpumask_remove_table(priv->cpus); + free_cpumask_var(priv->cpus); + list_del(&priv->list); + kfree(priv); + } +} + +static int __init airoha_cpufreq_driver_probe(void) +{ + int cpu, ret; + + if (!of_machine_is_compatible("airoha,en7581")) + return -ENODEV; + + for_each_possible_cpu(cpu) { + ret = airoha_cpufreq_driver_init_cpu(cpu); + if (ret) + goto err; + } + + ret = cpufreq_register_driver(&airoha_cpufreq_driver); + if (ret) + goto err; + + return 0; + +err: + airoha_cpufreq_release(); + return ret; +} +module_init(airoha_cpufreq_driver_probe); + +static void __exit airoha_cpufreq_driver_remove(void) +{ + cpufreq_unregister_driver(&airoha_cpufreq_driver); + airoha_cpufreq_release(); +} +module_exit(airoha_cpufreq_driver_remove); + +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>"); +MODULE_DESCRIPTION("CPUfreq driver for Airoha SoCs"); +MODULE_LICENSE("GPL"); diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 18942bfe9c95..5ecd8234bfac 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -103,6 +103,8 @@ static const struct of_device_id allowlist[] __initconst = { * platforms using "operating-points-v2" property. */ static const struct of_device_id blocklist[] __initconst = { + { .compatible = "airoha,en7581", }, + { .compatible = "allwinner,sun50i-h6", }, { .compatible = "allwinner,sun50i-h616", }, { .compatible = "allwinner,sun50i-h618", },
Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU frequency scaling with SMC APIs. All CPU share the same frequency and can't be controlled independently. Current shared CPU frequency is returned by the related SMC command. Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq driver is needed with OPP v2 nodes declared in DTS. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- Changes v2: - Fix kernel bot error with missing slab.h and bitfield.h header - Limit COMPILE_TEST to ARM64 due to smcc 1.2 drivers/cpufreq/Kconfig.arm | 8 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/airoha-cpufreq.c | 183 +++++++++++++++++++++++++++ drivers/cpufreq/cpufreq-dt-platdev.c | 2 + 4 files changed, 194 insertions(+) create mode 100644 drivers/cpufreq/airoha-cpufreq.c