| Message ID | 20241030185854.4015348-5-quic_jprakash@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for QCOM SPMI PMIC5 Gen3 ADC | expand |
Hi Jishnu, kernel test robot noticed the following build warnings: [auto build test WARNING on 6fb2fa9805c501d9ade047fc511961f3273cdcb5] url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20241031-030237 base: 6fb2fa9805c501d9ade047fc511961f3273cdcb5 patch link: https://lore.kernel.org/r/20241030185854.4015348-5-quic_jprakash%40quicinc.com patch subject: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20241102/202411021848.djIzD89X-lkp@intel.com/config) compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241102/202411021848.djIzD89X-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202411021848.djIzD89X-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:104:11: warning: format specifies type 'unsigned int' but the argument has type 'u8 *' (aka 'unsigned char *') [-Wformat] 103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n", | ~~~ | %s 104 | status, tm_status, tm_status[0], tm_status[1]); | ^~~~~~~~~ include/linux/dev_printk.h:165:39: note: expanded from macro 'dev_dbg' 165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__) | ~~~ ^~~~~~~~~~~ include/linux/dynamic_debug.h:274:19: note: expanded from macro 'dynamic_dev_dbg' 274 | dev, fmt, ##__VA_ARGS__) | ~~~ ^~~~~~~~~~~ include/linux/dynamic_debug.h:250:59: note: expanded from macro '_dynamic_func_call' 250 | _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__) | ^~~~~~~~~~~ include/linux/dynamic_debug.h:248:65: note: expanded from macro '_dynamic_func_call_cls' 248 | __dynamic_func_call_cls(__UNIQUE_ID(ddebug), cls, fmt, func, ##__VA_ARGS__) | ^~~~~~~~~~~ include/linux/dynamic_debug.h:224:15: note: expanded from macro '__dynamic_func_call_cls' 224 | func(&id, ##__VA_ARGS__); \ | ^~~~~~~~~~~ 1 warning generated. vim +104 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c 66 67 static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id) 68 { 69 struct adc_tm5_gen3_chip *adc_tm5 = dev_id; 70 u8 status, tm_status[2], val; 71 int ret, sdam_num; 72 73 sdam_num = get_sdam_from_irq(adc_tm5, irq); 74 if (sdam_num < 0) { 75 dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", irq); 76 return IRQ_HANDLED; 77 } 78 79 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, &status, 1); 80 if (ret) { 81 dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret); 82 return IRQ_HANDLED; 83 } 84 85 if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { 86 dev_err_ratelimited(adc_tm5->dev, "Unexpected conversion fault, status:%#x\n", 87 status); 88 val = ADC5_GEN3_CONV_ERR_CLR_REQ; 89 adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, 90 1); 91 return IRQ_HANDLED; 92 } 93 94 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2); 95 if (ret) { 96 dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); 97 return IRQ_HANDLED; 98 } 99 100 if (tm_status[0] || tm_status[1]) 101 schedule_work(&adc_tm5->tm_handler_work); 102 103 dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n", > 104 status, tm_status, tm_status[0], tm_status[1]); 105 106 return IRQ_HANDLED; 107 } 108
Hi Jishnu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 6fb2fa9805c501d9ade047fc511961f3273cdcb5]
url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20241031-030237
base: 6fb2fa9805c501d9ade047fc511961f3273cdcb5
patch link: https://lore.kernel.org/r/20241030185854.4015348-5-quic_jprakash%40quicinc.com
patch subject: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20241102/202411021924.bHINpnCr-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241102/202411021924.bHINpnCr-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411021924.bHINpnCr-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:599,
from include/asm-generic/bug.h:22,
from arch/x86/include/asm/bug.h:99,
from include/linux/bug.h:5,
from include/linux/fortify-string.h:6,
from include/linux/string.h:390,
from arch/x86/include/asm/page_32.h:18,
from arch/x86/include/asm/page.h:14,
from arch/x86/include/asm/processor.h:20,
from include/linux/sched.h:13,
from include/linux/ratelimit.h:6,
from include/linux/dev_printk.h:16,
from include/linux/device.h:15,
from include/linux/auxiliary_bus.h:11,
from include/linux/iio/adc/qcom-adc5-gen3-common.h:12,
from drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:7:
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c: In function 'adctm5_gen3_isr':
>> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:103:31: warning: format '%x' expects argument of type 'unsigned int', but argument 5 has type 'u8 *' {aka 'unsigned char *'} [-Wformat=]
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:224:29: note: in definition of macro '__dynamic_func_call_cls'
224 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:250:9: note: in expansion of macro '_dynamic_func_call_cls'
250 | _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:273:9: note: in expansion of macro '_dynamic_func_call'
273 | _dynamic_func_call(fmt, __dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:165:9: note: in expansion of macro 'dynamic_dev_dbg'
165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:165:30: note: in expansion of macro 'dev_fmt'
165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:103:9: note: in expansion of macro 'dev_dbg'
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ^~~~~~~
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:103:66: note: format string is defined here
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ~~^
| |
| unsigned int
| %#hhn
--
>> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:22: warning: Cannot understand * @adc_tm: indicates if the channel is used for TM measurements.
on line 22 - I thought it was a doc line
vim +103 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
> 7 #include <linux/iio/adc/qcom-adc5-gen3-common.h>
8 #include <linux/iio/consumer.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/thermal.h>
15 #include <linux/unaligned.h>
16
17 #include "../thermal_hwmon.h"
18
19 struct adc_tm5_gen3_chip;
20
21 /**
> 22 * @adc_tm: indicates if the channel is used for TM measurements.
23 * @tm_chan_index: TM channel number used (ranging from 1-7).
24 * @timer: time period of recurring TM measurement.
25 * @tzd: pointer to thermal device corresponding to TM channel.
26 * @high_thr_en: TM high threshold crossing detection enabled.
27 * @low_thr_en: TM low threshold crossing detection enabled.
28 * @last_temp: last temperature that caused threshold violation,
29 * or a thermal TM channel.
30 * @last_temp_set: indicates if last_temp is stored.
31 */
32
33 struct adc_tm5_gen3_channel_props {
34 struct device *dev;
35 unsigned int timer;
36 unsigned int tm_chan_index;
37 unsigned int sdam_index;
38 struct adc5_channel_common_prop common_props;
39 bool high_thr_en;
40 bool low_thr_en;
41 bool meas_en;
42 struct adc_tm5_gen3_chip *chip;
43 struct thermal_zone_device *tzd;
44 int last_temp;
45 bool last_temp_set;
46 };
47
48 struct adc_tm5_gen3_chip {
49 struct adc5_device_data *dev_data;
50 struct adc_tm5_gen3_channel_props *chan_props;
51 unsigned int nchannels;
52 struct device *dev;
53 struct work_struct tm_handler_work;
54 };
55
56 static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq)
57 {
58 int i;
59
60 for (i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
61 if (adc_tm5->dev_data->base[i].irq == irq)
62 return i;
63 }
64 return -ENOENT;
65 }
66
67 static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id)
68 {
69 struct adc_tm5_gen3_chip *adc_tm5 = dev_id;
70 u8 status, tm_status[2], val;
71 int ret, sdam_num;
72
73 sdam_num = get_sdam_from_irq(adc_tm5, irq);
74 if (sdam_num < 0) {
75 dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", irq);
76 return IRQ_HANDLED;
77 }
78
79 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
80 if (ret) {
81 dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret);
82 return IRQ_HANDLED;
83 }
84
85 if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
86 dev_err_ratelimited(adc_tm5->dev, "Unexpected conversion fault, status:%#x\n",
87 status);
88 val = ADC5_GEN3_CONV_ERR_CLR_REQ;
89 adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val,
90 1);
91 return IRQ_HANDLED;
92 }
93
94 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
95 if (ret) {
96 dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret);
97 return IRQ_HANDLED;
98 }
99
100 if (tm_status[0] || tm_status[1])
101 schedule_work(&adc_tm5->tm_handler_work);
102
> 103 dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
104 status, tm_status, tm_status[0], tm_status[1]);
105
106 return IRQ_HANDLED;
107 }
108
Hi Krzysztof, On 10/31/2024 4:30 PM, Krzysztof Kozlowski wrote: > On 30/10/2024 19:58, Jishnu Prakash wrote: >> Add support for ADC_TM part of PMIC5 Gen3. >> >> This is an auxiliary driver under the Gen3 ADC driver, which >> implements the threshold setting and interrupt generating >> functionalities of QCOM ADC_TM drivers, used to support thermal >> trip points. >> >> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> >> --- >> drivers/thermal/qcom/Kconfig | 11 + >> drivers/thermal/qcom/Makefile | 1 + >> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 489 ++++++++++++++++++ >> 3 files changed, 501 insertions(+) >> create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c >> >> diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig >> index 2c7f3f9a26eb..f9876fb8606d 100644 >> --- a/drivers/thermal/qcom/Kconfig >> +++ b/drivers/thermal/qcom/Kconfig >> @@ -21,6 +21,17 @@ config QCOM_SPMI_ADC_TM5 >> Thermal client sets threshold temperature for both warm and cool and >> gets updated when a threshold is reached. >> >> +config QCOM_SPMI_ADC_TM5_GEN3 >> + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3" >> + depends on OF && SPMI && IIO && QCOM_SPMI_ADC5_GEN3 > > || COMPILE_TEST won't work? Checking again, it looks like most of these dependencies are not needed and making it dependent on QCOM_SPMI_ADC5_GEN3 alone should be sufficient. Will update this in the next patch version. > >> + select REGMAP_SPMI >> + select QCOM_VADC_COMMON >> + help >> + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal >> + monitoring device. It shows up as a thermal zone with multiple trip points. >> + Thermal client sets threshold temperature for both warm and cool and >> + gets updated when a threshold is reached. >> + > > > ... > >> + >> +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = { >> + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", }, >> + {}, >> +}; >> + >> +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table); >> + >> +static struct adc_tm5_auxiliary_drv adctm5gen3_auxiliary_drv = { >> + .adrv = { >> + .id_table = adctm5_auxiliary_id_table, >> + .probe = adc_tm5_probe, >> + }, >> + .tm_event_notify = adctm_event_handler, >> +}; >> + >> +static int __init adctm5_init_module(void) >> +{ >> + return auxiliary_driver_register(&adctm5gen3_auxiliary_drv.adrv); >> +} >> + >> +static void __exit adctm5_exit_module(void) >> +{ >> + auxiliary_driver_unregister(&adctm5gen3_auxiliary_drv.adrv); >> +} >> + >> +module_init(adctm5_init_module); >> +module_exit(adctm5_exit_module); > > Why not module_auxiliary_driver? module_auxiliary_driver should work, will update it in next patch version. Thanks, Jishnu > > > Best regards, > Krzysztof >
diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index 2c7f3f9a26eb..f9876fb8606d 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -21,6 +21,17 @@ config QCOM_SPMI_ADC_TM5 Thermal client sets threshold temperature for both warm and cool and gets updated when a threshold is reached. +config QCOM_SPMI_ADC_TM5_GEN3 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3" + depends on OF && SPMI && IIO && QCOM_SPMI_ADC5_GEN3 + select REGMAP_SPMI + select QCOM_VADC_COMMON + help + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal + monitoring device. It shows up as a thermal zone with multiple trip points. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 0fa2512042e7..828d9e7bc797 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) += qcom-spmi-adc-tm5-gen3.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o obj-$(CONFIG_QCOM_LMH) += lmh.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c new file mode 100644 index 000000000000..fa57f417d833 --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/bitfield.h> +#include <linux/iio/adc/qcom-adc5-gen3-common.h> +#include <linux/iio/consumer.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/thermal.h> +#include <linux/unaligned.h> + +#include "../thermal_hwmon.h" + +struct adc_tm5_gen3_chip; + +/** + * @adc_tm: indicates if the channel is used for TM measurements. + * @tm_chan_index: TM channel number used (ranging from 1-7). + * @timer: time period of recurring TM measurement. + * @tzd: pointer to thermal device corresponding to TM channel. + * @high_thr_en: TM high threshold crossing detection enabled. + * @low_thr_en: TM low threshold crossing detection enabled. + * @last_temp: last temperature that caused threshold violation, + * or a thermal TM channel. + * @last_temp_set: indicates if last_temp is stored. + */ + +struct adc_tm5_gen3_channel_props { + struct device *dev; + unsigned int timer; + unsigned int tm_chan_index; + unsigned int sdam_index; + struct adc5_channel_common_prop common_props; + bool high_thr_en; + bool low_thr_en; + bool meas_en; + struct adc_tm5_gen3_chip *chip; + struct thermal_zone_device *tzd; + int last_temp; + bool last_temp_set; +}; + +struct adc_tm5_gen3_chip { + struct adc5_device_data *dev_data; + struct adc_tm5_gen3_channel_props *chan_props; + unsigned int nchannels; + struct device *dev; + struct work_struct tm_handler_work; +}; + +static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq) +{ + int i; + + for (i = 0; i < adc_tm5->dev_data->num_sdams; i++) { + if (adc_tm5->dev_data->base[i].irq == irq) + return i; + } + return -ENOENT; +} + +static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id) +{ + struct adc_tm5_gen3_chip *adc_tm5 = dev_id; + u8 status, tm_status[2], val; + int ret, sdam_num; + + sdam_num = get_sdam_from_irq(adc_tm5, irq); + if (sdam_num < 0) { + dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", irq); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, &status, 1); + if (ret) { + dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(adc_tm5->dev, "Unexpected conversion fault, status:%#x\n", + status); + val = ADC5_GEN3_CONV_ERR_CLR_REQ; + adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, + 1); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (tm_status[0] || tm_status[1]) + schedule_work(&adc_tm5->tm_handler_work); + + dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n", + status, tm_status, tm_status[0], tm_status[1]); + + return IRQ_HANDLED; +} + +static int adc5_gen3_tm_status_check(struct adc_tm5_gen3_chip *adc_tm5, + int sdam_index, u8 *tm_status, u8 *buf) +{ + int ret; + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS, tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return ret; + } + + ret = adc5_gen3_status_clear(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc status clear conv_req failed with %d\n", ret); + return ret; + } + + ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_CH_DATA0(0), buf, 16); + if (ret) + dev_err(adc_tm5->dev, "adc read data failed with %d\n", ret); + + return ret; +} + +static void tm_handler_work(struct work_struct *work) +{ + struct adc_tm5_gen3_chip *adc_tm5 = container_of(work, struct adc_tm5_gen3_chip, + tm_handler_work); + struct adc_tm5_gen3_channel_props *chan_prop; + u8 tm_status[2] = {0}; + u8 buf[16] = {0}; + int i, ret = 0, sdam_index = -1; + + for (i = 0; i < adc_tm5->nchannels; i++) { + bool upper_set = false, lower_set = false; + int temp, offset; + u16 code = 0; + + chan_prop = &adc_tm5->chan_props[i]; + offset = chan_prop->tm_chan_index; + + adc5_take_mutex_lock(adc_tm5->dev, true); + if (chan_prop->sdam_index != sdam_index) { + sdam_index = chan_prop->sdam_index; + ret = adc5_gen3_tm_status_check(adc_tm5, sdam_index, tm_status, buf); + if (ret) { + adc5_take_mutex_lock(adc_tm5->dev, false); + break; + } + } + + if ((tm_status[0] & BIT(offset)) && chan_prop->high_thr_en) + upper_set = true; + + if ((tm_status[1] & BIT(offset)) && chan_prop->low_thr_en) + lower_set = true; + adc5_take_mutex_lock(adc_tm5->dev, false); + + if (!(upper_set || lower_set)) + continue; + + code = get_unaligned_le16(&buf[2 * offset]); + pr_debug("ADC_TM threshold code:%#x\n", code); + + ret = adc5_gen3_therm_code_to_temp(adc_tm5->dev, &chan_prop->common_props, code, + &temp); + if (ret) { + dev_err(adc_tm5->dev, "Invalid temperature reading, ret = %d, code=%#x\n", + ret, code); + continue; + } + + chan_prop->last_temp = temp; + chan_prop->last_temp_set = true; + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED); + } +} + +static int adc_tm5_gen3_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 = prop->chip; + + if (prop->last_temp_set) { + pr_debug("last_temp: %d\n", prop->last_temp); + prop->last_temp_set = false; + *temp = prop->last_temp; + return 0; + } + + return adc5_gen3_get_scaled_reading(adc_tm5->dev, &prop->common_props, temp); +} + +static int _adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop) +{ + struct adc_tm5_gen3_chip *adc_tm5 = prop->chip; + int ret; + u8 val; + + prop->high_thr_en = false; + prop->low_thr_en = false; + + ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret) + return ret; + + val = BIT(prop->tm_chan_index); + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, + &val, 1); + if (ret) + return ret; + + val = MEAS_INT_DISABLE; + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_TIMER_SEL, &val, 1); + if (ret) + return ret; + + /* To indicate there is an actual conversion request */ + val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) + return ret; + + val = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); +} + +static int adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop) +{ + return _adc_tm5_gen3_disable_channel(prop); +} + +# define ADC_TM5_GEN3_CONFIG_REGS 12 + +static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_chip *adc_tm5 = prop->chip; + u8 conv_req = 0, buf[ADC_TM5_GEN3_CONFIG_REGS]; + u16 adc_code; + int ret; + + ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret < 0) + return ret; + + ret = adc5_gen3_read(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Write SID */ + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid); + + /* + * Select TM channel and indicate there is an actual + * conversion request + */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + + buf[2] = prop->timer; + + /* Digital param selection */ + adc5_gen3_update_dig_param(&prop->common_props, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->common_props.avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->common_props.channel; + + /* Select HW settle delay for channel */ + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->common_props.hw_settle_time); + + /* High temperature corresponds to low voltage threshold */ + if (high_temp != INT_MAX) { + prop->low_thr_en = true; + adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp); + put_unaligned_le16(adc_code, &buf[8]); + } else { + prop->low_thr_en = false; + } + + /* Low temperature corresponds to high voltage threshold */ + if (low_temp != -INT_MAX) { + prop->high_thr_en = true; + adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp); + put_unaligned_le16(adc_code, &buf[10]); + } else { + prop->high_thr_en = false; + } + + buf[7] = 0; + if (prop->high_thr_en) + buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN; + if (prop->low_thr_en) + buf[7] |= ADC5_GEN3_LOW_THR_INT_EN; + + ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, + 1); +} + +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + int ret; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 = prop->chip; + + dev_dbg(adc_tm5->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n", + prop->common_props.label, low_temp, high_temp); + + adc5_take_mutex_lock(adc_tm5->dev, true); + if (high_temp == INT_MAX && low_temp <= -INT_MAX) + ret = adc_tm5_gen3_disable_channel(prop); + else + ret = adc_tm5_gen3_configure(prop, low_temp, high_temp); + adc5_take_mutex_lock(adc_tm5->dev, false); + + return ret; +} + +static const struct thermal_zone_device_ops adc_tm_ops = { + .get_temp = adc_tm5_gen3_get_temp, + .set_trips = adc_tm5_gen3_set_trip_temp, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5) +{ + unsigned int i, channel; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc_tm5->nchannels; i++) { + channel = V_CHAN(adc_tm5->chan_props[i].common_props); + tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel, + &adc_tm5->chan_props[i], &adc_tm_ops); + + if (IS_ERR(tzd)) { + if (PTR_ERR(tzd) == -ENODEV) { + dev_warn(adc_tm5->dev, "thermal sensor on channel %d is not used\n", + channel); + continue; + } + return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd), + "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), channel); + } + adc_tm5->chan_props[i].tzd = tzd; + devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd); + } + return 0; +} + +static void adc5_gen3_clear_work(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 = data; + + cancel_work_sync(&adc_tm5->tm_handler_work); +} + +static void adc5_gen3_disable(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 = data; + int i; + + adc5_take_mutex_lock(adc_tm5->dev, true); + /* Disable all available TM channels */ + for (i = 0; i < adc_tm5->nchannels; i++) + _adc_tm5_gen3_disable_channel(&adc_tm5->chan_props[i]); + + adc5_take_mutex_lock(adc_tm5->dev, false); +} + +static void adctm_event_handler(struct auxiliary_device *adev) +{ + struct adc_tm5_gen3_chip *adc_tm5 = auxiliary_get_drvdata(adev); + + schedule_work(&adc_tm5->tm_handler_work); +} + +static int adc_tm5_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *id) +{ + struct adc_tm5_gen3_chip *adc_tm5; + struct tm5_aux_dev_wrapper *aux_dev_wrapper; + struct device *dev = &aux_dev->dev; + int i, ret; + + adc_tm5 = devm_kzalloc(&aux_dev->dev, sizeof(*adc_tm5), GFP_KERNEL); + if (!adc_tm5) + return -ENOMEM; + + aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, aux_dev); + + adc_tm5->dev = dev; + adc_tm5->dev_data = aux_dev_wrapper->dev_data; + adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels; + adc_tm5->chan_props = devm_kcalloc(adc_tm5->dev, aux_dev_wrapper->n_tm_channels, + sizeof(*adc_tm5->chan_props), GFP_KERNEL); + if (!adc_tm5->chan_props) + return -ENOMEM; + + for (i = 0; i < adc_tm5->nchannels; i++) { + adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i]; + adc_tm5->chan_props[i].timer = MEAS_INT_1S; + adc_tm5->chan_props[i].sdam_index = (i + 1) / 8; + adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8; + adc_tm5->chan_props[i].chip = adc_tm5; + } + + ret = devm_add_action_or_reset(adc_tm5->dev, adc5_gen3_disable, adc_tm5); + if (ret) + return ret; + + for (i = 1; i < adc_tm5->dev_data->num_sdams; i++) { + ret = devm_request_threaded_irq(adc_tm5->dev, adc_tm5->dev_data->base[i].irq, NULL, + adctm5_gen3_isr, IRQF_ONESHOT, + adc_tm5->dev_data->base[i].irq_name, adc_tm5); + if (ret < 0) + return ret; + } + + INIT_WORK(&adc_tm5->tm_handler_work, tm_handler_work); + ret = devm_add_action(adc_tm5->dev, adc5_gen3_clear_work, adc_tm5); + if (ret) + return ret; + + ret = adc_tm5_register_tzd(adc_tm5); + if (ret) + return ret; + + auxiliary_set_drvdata(aux_dev, adc_tm5); + return 0; +} + +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = { + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", }, + {}, +}; + +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table); + +static struct adc_tm5_auxiliary_drv adctm5gen3_auxiliary_drv = { + .adrv = { + .id_table = adctm5_auxiliary_id_table, + .probe = adc_tm5_probe, + }, + .tm_event_notify = adctm_event_handler, +}; + +static int __init adctm5_init_module(void) +{ + return auxiliary_driver_register(&adctm5gen3_auxiliary_drv.adrv); +} + +static void __exit adctm5_exit_module(void) +{ + auxiliary_driver_unregister(&adctm5gen3_auxiliary_drv.adrv); +} + +module_init(adctm5_init_module); +module_exit(adctm5_exit_module); + +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_ADC5_GEN3);
Add support for ADC_TM part of PMIC5 Gen3. This is an auxiliary driver under the Gen3 ADC driver, which implements the threshold setting and interrupt generating functionalities of QCOM ADC_TM drivers, used to support thermal trip points. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> --- drivers/thermal/qcom/Kconfig | 11 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 489 ++++++++++++++++++ 3 files changed, 501 insertions(+) create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c