| Message ID | 20241112172022.88348-3-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Convert nanoMIPS LSA opcode to decodetree | expand |
On 12/11/24 18:20, Philippe Mathieu-Daudé wrote: > From: Philippe Mathieu-Daudé <f4bug@amsat.org> > > Introduce the nanoMIPS decodetree configs for the 16-bit > and 32-bit instructions. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/mips/tcg/translate.h | 2 ++ > target/mips/tcg/nanomips16.decode | 8 ++++++++ > target/mips/tcg/nanomips32.decode | 8 ++++++++ > target/mips/tcg/nanomips_translate.c | 14 ++++++++++++++ > target/mips/tcg/nanomips_translate.c.inc | 7 +++++++ > target/mips/tcg/meson.build | 3 +++ > 6 files changed, 42 insertions(+) > create mode 100644 target/mips/tcg/nanomips16.decode > create mode 100644 target/mips/tcg/nanomips32.decode > create mode 100644 target/mips/tcg/nanomips_translate.c > diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c > new file mode 100644 > index 0000000000..c148c13ed9 > --- /dev/null > +++ b/target/mips/tcg/nanomips_translate.c > @@ -0,0 +1,14 @@ > +/* > + * MIPS emulation for QEMU - nanoMIPS translation routines > + * > + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org> > + * > + * SPDX-License-Identifier: LGPL-2.1-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "translate.h" > + > +/* Include the auto-generated decoders. */ > +#include "decode-nanomips16.c.inc" > +#include "decode-nanomips32.c.inc" > diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc > index 1e274143bb..e401b92bfd 100644 > --- a/target/mips/tcg/nanomips_translate.c.inc > +++ b/target/mips/tcg/nanomips_translate.c.inc > @@ -4482,6 +4482,13 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) > return 2; > } > > + if (decode_isa_nanomips16(ctx, ctx->opcode)) { > + return 2; > + } > + if (decode_isa_nanomips32(ctx, ctx->opcode)) { This call is incorrect, the caller previously called translator_lduw() so ctx->opcode is incomplete. > + return 4; > + } Discarding this series for now.
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 816453f2be..a91c003f96 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -224,6 +224,8 @@ bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); +bool decode_isa_nanomips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_nanomips32(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode new file mode 100644 index 0000000000..81fdc68e98 --- /dev/null +++ b/target/mips/tcg/nanomips16.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode new file mode 100644 index 0000000000..9cecf1e13d --- /dev/null +++ b/target/mips/tcg/nanomips32.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c new file mode 100644 index 0000000000..c148c13ed9 --- /dev/null +++ b/target/mips/tcg/nanomips_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - nanoMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org> + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-nanomips16.c.inc" +#include "decode-nanomips32.c.inc" diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 1e274143bb..e401b92bfd 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4482,6 +4482,13 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) return 2; } + if (decode_isa_nanomips16(ctx, ctx->opcode)) { + return 2; + } + if (decode_isa_nanomips32(ctx, ctx->opcode)) { + return 4; + } + op = extract32(ctx->opcode, 10, 6); switch (op) { case NM_P16_MV: diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 5db5681eb1..f815174ed1 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -2,6 +2,8 @@ gen = [ decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']), decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), + decodetree.process('nanomips16.decode', extra_args: ['--decode=decode_isa_nanomips16', '--insnwidth=16']), + decodetree.process('nanomips32.decode', extra_args: ['--decode=decode_isa_nanomips32']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), @@ -21,6 +23,7 @@ mips_ss.add(files( 'micromips_translate.c', 'msa_helper.c', 'msa_translate.c', + 'nanomips_translate.c', 'op_helper.c', 'rel6_translate.c', 'translate.c',