| Message ID | 20241113055830.2918347-3-quic_yrangana@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add QCrypto support for QCS8300 | expand |
On 13.11.2024 6:58 AM, Yuvaraj Ranganathan wrote: > Add the QCE and Crypto BAM DMA nodes. > > Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 2c35f96c3f28..d7007e175c15 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -710,6 +710,30 @@ ufs_mem_phy: phy@1d87000 { > status = "disabled"; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0x0 0x01dc4000 0x0 0x28000>; > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <20>; > + qcom,num-ees = <4>; > + iommus = <&apps_smmu 0x480 0x00>, > + <&apps_smmu 0x481 0x00>; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,qcs8300-qce", "qcom,qce"; > + reg = <0x0 0x01dfa000 0x0 0x6000>; > + dmas = <&cryptobam 4>, <&cryptobam 5>; > + dma-names = "rx", "tx"; > + iommus = <&apps_smmu 0x480 0x00>, > + <&apps_smmu 0x481 0x00>; > + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; QCOM_ICC_TAG_ALWAYS Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f28..d7007e175c15 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -710,6 +710,30 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + iommus = <&apps_smmu 0x480 0x00>, + <&apps_smmu 0x481 0x00>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,qcs8300-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x00>, + <&apps_smmu 0x481 0x00>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;
Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)