diff mbox series

[RISU] risugen/aarch64: SMULH and UMULH require ra == 31

Message ID 20241116053918.420404-1-richard.henderson@linaro.org
State New
Headers show
Series [RISU] risugen/aarch64: SMULH and UMULH require ra == 31 | expand

Commit Message

Richard Henderson Nov. 16, 2024, 5:39 a.m. UTC 
Do not generate ra other than 31, as it is UNPREDICTABLE
whether the instruction will trap as invalid.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 aarch64.risu | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Peter Maydell Nov. 18, 2024, 10:33 a.m. UTC | #1 
On Sat, 16 Nov 2024 at 05:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Do not generate ra other than 31, as it is UNPREDICTABLE
> whether the instruction will trap as invalid.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Applied to risu upstream, thanks.

-- PMM
diff mbox series

Patch

diff --git a/aarch64.risu b/aarch64.risu
index 8f08cd0..87d9c72 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -1887,7 +1887,7 @@  SMSUBL A64 1 00 11011 001 rm:5 1 ra:5 rn:5 rd:5 \
 
 SMNEGL A64 1 00 11011 001 rm:5 1 11111 rn:5 rd:5
 
-SMULH A64 1 00 11011 010 rm:5 0 ra:5 rn:5 rd:5
+SMULH A64 1 00 11011 010 rm:5 0 11111 rn:5 rd:5
 
 UMADDL A64 1 00 11011 101 rm:5 0 ra:5 rn:5 rd:5 \
 !constraints { $ra != 31; }
@@ -1899,7 +1899,7 @@  UMSUBL A64 1 00 11011 101 rm:5 1 ra:5 rn:5 rd:5 \
 
 UMNEGL A64 1 00 11011 101 rm:5 1 11111 rn:5 rd:5
 
-UMULH A64 1 00 11011 110 rm:5 0 ra:5 rn:5 rd:5
+UMULH A64 1 00 11011 110 rm:5 0 11111 rn:5 rd:5
 
 # - Logical (shifted register)
 # 31|30 29| 28 27 26 25 24 |23 22| 21| 20    16 15      10 9    5 4    0