| Message ID | 20241120091507.1404368-8-quic_mdalam@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add QPIC SPI NAND driver | expand |
On 20.11.2024 10:15 AM, Md Sadre Alam wrote: > Add SPI NAND support for ipq9574 SoC. > > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > --- [...] Feel free to put dt patches in a separate series after Miquel picks up the mtd changes > &usb_0_dwc3 { > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index d1fd35ebc4a2..45fb26bc9480 100644 board and dtsi patches should be 2 separate ones > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { > reg = <0x01937000 0x21000>; > }; > > + qpic_bam: dma-controller@7984000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x7984000 0x1c000>; Please pad the address part to 8 hex digits with leading zeroes > + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QPIC_AHB_CLK>; > + clock-names = "bam_clk"; > + #dma-cells = <1>; > + qcom,ee = <0>; > + status = "disabled"; > + }; > + > + qpic_nand: spi@79b0000 { > + compatible = "qcom,ipq9574-snand"; > + reg = <0x79b0000 0x10000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QPIC_CLK>, > + <&gcc GCC_QPIC_AHB_CLK>, > + <&gcc GCC_QPIC_IO_MACRO_CLK>; > + clock-names = "core", "aon", "iom"; > + dmas = <&qpic_bam 0>, > + <&qpic_bam 1>, > + <&qpic_bam 2>; > + dma-names = "tx", "rx", "cmd"; Please make clock/dma names a vertical list, like clocks/dmas Also, is it okay not to use any of the GCC_QPIC_BCR/ GCC_QPIC_AHB_ARES/GCC_QPIC_ARES resets found in GCC? Konrad
On 12/5/2024 10:49 PM, Konrad Dybcio wrote: > On 20.11.2024 10:15 AM, Md Sadre Alam wrote: >> Add SPI NAND support for ipq9574 SoC. >> >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> --- > > [...] > > Feel free to put dt patches in a separate series after Miquel picks > up the mtd changes Ok > >> &usb_0_dwc3 { >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index d1fd35ebc4a2..45fb26bc9480 100644 > > board and dtsi patches should be 2 separate ones Ok > >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { >> reg = <0x01937000 0x21000>; >> }; >> >> + qpic_bam: dma-controller@7984000 { >> + compatible = "qcom,bam-v1.7.0"; >> + reg = <0x7984000 0x1c000>; > > Please pad the address part to 8 hex digits with leading zeroes Ok > >> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QPIC_AHB_CLK>; >> + clock-names = "bam_clk"; >> + #dma-cells = <1>; >> + qcom,ee = <0>; >> + status = "disabled"; >> + }; >> + >> + qpic_nand: spi@79b0000 { >> + compatible = "qcom,ipq9574-snand"; >> + reg = <0x79b0000 0x10000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&gcc GCC_QPIC_CLK>, >> + <&gcc GCC_QPIC_AHB_CLK>, >> + <&gcc GCC_QPIC_IO_MACRO_CLK>; >> + clock-names = "core", "aon", "iom"; >> + dmas = <&qpic_bam 0>, >> + <&qpic_bam 1>, >> + <&qpic_bam 2>; >> + dma-names = "tx", "rx", "cmd"; > > Please make clock/dma names a vertical list, like clocks/dmas Ok > > Also, is it okay not to use any of the GCC_QPIC_BCR/ > GCC_QPIC_AHB_ARES/GCC_QPIC_ARES resets found in GCC? It's recommended by HW team, will check once again with HW team. > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..6429a6b3b903 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { drive-strength = <8>; bias-pull-up; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins = "gpio5"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio4"; + function = "qspi_cs"; + drive-strength = <8>; + bias-disable; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; }; &usb_0_dwc3 { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index d1fd35ebc4a2..45fb26bc9480 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x7984000 0x1c000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x79b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>,
Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> --- Change in [v14] * No change Change in [v13] * No change Change in [v12] * No change Change in [v11] * No change Change in [v10] * No change Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Updated gpio number as per pin control driver * Fixed alignment issue Change in [v2] * Added initial enablement for spi-nand Change in [v1] * Posted as RFC patch for design review .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ 2 files changed, 70 insertions(+)