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[RFC,v1,12/14] riscv: dts: Add Video Output clock and syscon regmap nodes

Message ID 20241203134137.2114847-13-m.wilczynski@samsung.com
State New
Headers show
Series Enable drm/imagination BXM-4-64 Support for LicheePi 4A | expand

Commit Message

Michal Wilczynski Dec. 3, 2024, 1:41 p.m. UTC 
The address space controlling the Video Output (VO) subsystem clocks
also contains control registers for GPU resets. To properly synchronize
access to this shared address space, create a syscon Device Tree node
for the VO registers and reference it in the clock controller node.

This change ensures coordinated access to the VO registers between the
clock controller and other drivers, preventing conflicts and maintaining
system stability.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index dc2d554b4a71..39d39059160d 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -489,6 +489,18 @@  clk: clock-controller@ffef010000 {
 			#clock-cells = <1>;
 		};
 
+		vosys_clk: clock-controller {
+			compatible = "thead,th1520-clk-vo";
+			thead,vosys-regmap = <&vosys_reg>;
+			#clock-cells = <1>;
+		};
+
+		vosys_reg: vosys@ffef528000 {
+			compatible = "thead,th1520-vosys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
 		dmac0: dma-controller@ffefc00000 {
 			compatible = "snps,axi-dma-1.01a";
 			reg = <0xff 0xefc00000 0x0 0x1000>;