| Message ID | 20241213095237.1409174-9-quic_prashk@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Disable USB U1/U2 entry for QC targets | expand |
On 13.12.2024 10:52 AM, Prashanth K wrote: > From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > > Disable U1 and U2 power-saving states to improve stability of USB. > These low-power link states, designed to reduce power consumption > during idle periods, can cause issues in latency-sensitive or high > throughput use cases. Over the years, some of the issues seen are > as follows: > > 1. In device mode of operation, when UVC is active, enabling U1/U2 > is sometimes causing packets drops due to delay in entry/exit of > intermittent these low power states. These packet drops are often > reflected as missed isochronous transfers, as the controller wasn't > able to send packet in that microframe interval and hence glitches > are seen on the final transmitted video output. > > 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable > when U1/U2 is enabled. Often when link enters U2, there is a re- > enumeration seen and device is unusable for many use cases. > > 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when > the cable is disconnected and reconnected to host PC in HS, there > is no link status change interrupt seen and the plug-in in HS doesn't > show up a bus reset and enumeration failure happens. > > Disabling these intermittent power states enhances device stability > without affecting power usage. > > Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > Signed-off-by: Prashanth K <quic_prashk@quicinc.com> > --- [...] > > @@ -3570,6 +3576,8 @@ tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x20000>; > #hwlock-cells = <1>; > + snps,dis-u1-entry-quirk; > + snps,dis-u2-entry-quirk; Oh? Konrad
On 14-12-24 05:36 am, Konrad Dybcio wrote: > On 13.12.2024 10:52 AM, Prashanth K wrote: >> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> >> >> Disable U1 and U2 power-saving states to improve stability of USB. >> These low-power link states, designed to reduce power consumption >> during idle periods, can cause issues in latency-sensitive or high >> throughput use cases. Over the years, some of the issues seen are >> as follows: >> >> 1. In device mode of operation, when UVC is active, enabling U1/U2 >> is sometimes causing packets drops due to delay in entry/exit of >> intermittent these low power states. These packet drops are often >> reflected as missed isochronous transfers, as the controller wasn't >> able to send packet in that microframe interval and hence glitches >> are seen on the final transmitted video output. >> >> 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable >> when U1/U2 is enabled. Often when link enters U2, there is a re- >> enumeration seen and device is unusable for many use cases. >> >> 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when >> the cable is disconnected and reconnected to host PC in HS, there >> is no link status change interrupt seen and the plug-in in HS doesn't >> show up a bus reset and enumeration failure happens. >> >> Disabling these intermittent power states enhances device stability >> without affecting power usage. >> >> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> >> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> >> --- > > [...] > >> >> @@ -3570,6 +3576,8 @@ tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x0 0x01f40000 0x0 0x20000>; >> #hwlock-cells = <1>; >> + snps,dis-u1-entry-quirk; >> + snps,dis-u2-entry-quirk; > > Oh? > Thanks for pointing. I messed up, will update and send next version. Regards, Prashanth K
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9f315a51a7c1..7a50991daaa6 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3411,6 +3411,8 @@ usb_0_dwc3: usb@a600000 { iommus = <&apps_smmu 0x080 0x0>; phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; }; @@ -3500,6 +3502,8 @@ usb_1_dwc3: usb@a800000 { iommus = <&apps_smmu 0x0a0 0x0>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; }; @@ -3563,6 +3567,8 @@ usb_2_dwc3: usb@a400000 { iommus = <&apps_smmu 0x020 0x0>; phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; }; @@ -3570,6 +3576,8 @@ tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; tcsr: syscon@1fc0000 {