| Message ID | 20241213-qcs615-gpu-dt-v2-3-47f3b312b178@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Devicetree changes for QCS615's GPU | expand |
On Fri, Dec 13, 2024 at 05:01:05PM +0530, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add gpu and gmu nodes for qcs615 chipset. > Please resubmit this in a series together with the gpucc patch. Regards, Bjorn > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..dee5d3be4aa34dd64864b6fe32ad589abac99bb7 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -387,6 +387,11 @@ smem_region: smem@86000000 { > no-map; > hwlocks = <&tcsr_mutex 3>; > }; > + > + pil_gpu_mem: pil-gpu@97715000 { > + reg = <0x0 0x97715000 0x0 0x2000>; > + no-map; > + }; > }; > > soc: soc@0 { > @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state { > }; > }; > > + gpu: gpu@5000000 { > + compatible = "qcom,adreno-612.0", "qcom,adreno"; > + reg = <0x0 0x05000000 0x0 0x90000>; > + reg-names = "kgsl_3d0_reg_memory"; > + > + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>; > + clock-names = "core", > + "mem_iface", > + "alt_mem_iface", > + "gmu", > + "xo"; > + > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; > + > + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "gfx-mem"; > + > + iommus = <&adreno_smmu 0x0 0x401>; > + operating-points-v2 = <&gpu_opp_table>; > + power-domains = <&rpmhpd RPMHPD_CX>; > + qcom,gmu = <&rgmu>; > + > + #cooling-cells = <2>; > + > + status = "disabled"; > + > + gpu_zap_shader: zap-shader { > + memory-region = <&pil_gpu_mem>; > + }; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-435000000 { > + opp-hz = /bits/ 64 <435000000>; > + required-opps = <&rpmhpd_opp_svs>; > + opp-peak-kBps = <3000000>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <3975000>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <5287500>; > + }; > + > + opp-745000000 { > + opp-hz = /bits/ 64 <745000000>; > + required-opps = <&rpmhpd_opp_nom_l1>; > + opp-peak-kBps = <6075000>; > + }; > + > + opp-845000000 { > + opp-hz = /bits/ 64 <845000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + opp-peak-kBps = <7050000>; > + }; > + }; > + }; > + > + rgmu: rgmu@506a000 { > + compatible = "qcom,adreno-rgmu"; > + reg = <0x0 0x0506a000 0x0 0x34000>; > + reg-names = "gmu"; > + power-domains = <&gpucc CX_GDSC>, > + <&gpucc GX_GDSC>; > + power-domain-names = "cx", "gx"; > + > + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hfi", "gmu"; > + }; > + > gpucc: clock-controller@5090000 { > compatible = "qcom,qcs615-gpucc"; > reg = <0 0x5090000 0 0x9000>; > > -- > 2.45.2 >
On 1/9/2025 4:03 AM, Bjorn Andersson wrote: > On Fri, Dec 13, 2024 at 05:01:05PM +0530, Akhil P Oommen wrote: >> From: Jie Zhang <quic_jiezh@quicinc.com> >> >> Add gpu and gmu nodes for qcs615 chipset. >> > > Please resubmit this in a series together with the gpucc patch. Sure. I will send a new revision. -Akhil. > > Regards, > Bjorn > >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 88 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..dee5d3be4aa34dd64864b6fe32ad589abac99bb7 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -387,6 +387,11 @@ smem_region: smem@86000000 { >> no-map; >> hwlocks = <&tcsr_mutex 3>; >> }; >> + >> + pil_gpu_mem: pil-gpu@97715000 { >> + reg = <0x0 0x97715000 0x0 0x2000>; >> + no-map; >> + }; >> }; >> >> soc: soc@0 { >> @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state { >> }; >> }; >> >> + gpu: gpu@5000000 { >> + compatible = "qcom,adreno-612.0", "qcom,adreno"; >> + reg = <0x0 0x05000000 0x0 0x90000>; >> + reg-names = "kgsl_3d0_reg_memory"; >> + >> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, >> + <&gcc GCC_DDRSS_GPU_AXI_CLK>, >> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_CXO_CLK>; >> + clock-names = "core", >> + "mem_iface", >> + "alt_mem_iface", >> + "gmu", >> + "xo"; >> + >> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; >> + >> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "gfx-mem"; >> + >> + iommus = <&adreno_smmu 0x0 0x401>; >> + operating-points-v2 = <&gpu_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + qcom,gmu = <&rgmu>; >> + >> + #cooling-cells = <2>; >> + >> + status = "disabled"; >> + >> + gpu_zap_shader: zap-shader { >> + memory-region = <&pil_gpu_mem>; >> + }; >> + >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-435000000 { >> + opp-hz = /bits/ 64 <435000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + opp-peak-kBps = <3000000>; >> + }; >> + >> + opp-500000000 { >> + opp-hz = /bits/ 64 <500000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + opp-peak-kBps = <3975000>; >> + }; >> + >> + opp-650000000 { >> + opp-hz = /bits/ 64 <650000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + opp-peak-kBps = <5287500>; >> + }; >> + >> + opp-745000000 { >> + opp-hz = /bits/ 64 <745000000>; >> + required-opps = <&rpmhpd_opp_nom_l1>; >> + opp-peak-kBps = <6075000>; >> + }; >> + >> + opp-845000000 { >> + opp-hz = /bits/ 64 <845000000>; >> + required-opps = <&rpmhpd_opp_turbo>; >> + opp-peak-kBps = <7050000>; >> + }; >> + }; >> + }; >> + >> + rgmu: rgmu@506a000 { >> + compatible = "qcom,adreno-rgmu"; >> + reg = <0x0 0x0506a000 0x0 0x34000>; >> + reg-names = "gmu"; >> + power-domains = <&gpucc CX_GDSC>, >> + <&gpucc GX_GDSC>; >> + power-domain-names = "cx", "gx"; >> + >> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hfi", "gmu"; >> + }; >> + >> gpucc: clock-controller@5090000 { >> compatible = "qcom,qcs615-gpucc"; >> reg = <0 0x5090000 0 0x9000>; >> >> -- >> 2.45.2 >>
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..dee5d3be4aa34dd64864b6fe32ad589abac99bb7 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -387,6 +387,11 @@ smem_region: smem@86000000 { no-map; hwlocks = <&tcsr_mutex 3>; }; + + pil_gpu_mem: pil-gpu@97715000 { + reg = <0x0 0x97715000 0x0 0x2000>; + no-map; + }; }; soc: soc@0 { @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state { }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-612.0", "qcom,adreno"; + reg = <0x0 0x05000000 0x0 0x90000>; + reg-names = "kgsl_3d0_reg_memory"; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0x0 0x401>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + qcom,gmu = <&rgmu>; + + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <3975000>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5287500>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + opp-peak-kBps = <6075000>; + }; + + opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + required-opps = <&rpmhpd_opp_turbo>; + opp-peak-kBps = <7050000>; + }; + }; + }; + + rgmu: rgmu@506a000 { + compatible = "qcom,adreno-rgmu"; + reg = <0x0 0x0506a000 0x0 0x34000>; + reg-names = "gmu"; + power-domains = <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,qcs615-gpucc"; reg = <0 0x5090000 0 0x9000>;