@@ -164,6 +164,7 @@ enum dpu_enc_rc_states {
* clks and resources after IDLE_TIMEOUT time.
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
+ * @num_dscs: Number of DSCs in use
* @wide_bus_en: wide bus is enabled on this interface
* @dsc: drm_dsc_config pointer, for DSC-enabled encoders
*/
@@ -204,6 +205,7 @@ struct dpu_encoder_virt {
struct msm_display_topology topology;
u32 idle_timeout;
+ u32 num_dscs;
bool wide_bus_en;
@@ -622,9 +624,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
if (dpu_enc->phys_encs[i])
intf_count++;
- /* See dpu_encoder_get_topology, we only support 2:2:1 topology */
if (dpu_enc->dsc)
- num_dsc = 2;
+ num_dsc = dpu_enc->num_dscs;
return (num_dsc > 0) && (num_dsc > intf_count);
}
@@ -1261,6 +1262,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
}
+ dpu_enc->num_dscs = num_dsc;
dpu_enc->dsc_mask = dsc_mask;
if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
If DSC is enabled, the only case is with 2 DSC engines so far. More usage case will be added, such as 4 DSC in 4:4:2 topoplogy. So get real number of DSCs to decide whether DSC merge is needed. Signed-off-by: Jun Nie <jun.nie@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)