| Message ID | 20241227-a133-display-support-v1-10-abad35b3579c@linumiz.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for A100/A133 display | expand |
On Fri, 27 Dec 2024 18:30:59 +0530 Parthiban Nallathambi <parthiban@linumiz.com> wrote: Hi, since LinusW wants to pull this already, I gave it a look, despite this series being not complete. > lvds, lcd, dsi all shares the same GPIO D bank and lvds0 > data 3 lines and lvds1 pins are missed, add them. > > Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> > --- > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c > index df90c75fb3c5..b97de80ae2f3 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c > @@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = { > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ > + SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */ I initially stumbled upon those first two pins being from lvds0, with the other 8 pins missing for this interface, but then realised that those are on portD, and we already describe them in this table (above). So those two were missing all the time. So having compared these lines to the A133 user manual, I can now say that they are all correct: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Linus, in contrast to what I originally thought, this patch *is* fine, so feel free to keep it in your tree. Sorry for the noise! Cheers, Andre > SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ > + SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */ > SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */ > SUNXI_FUNCTION(0x4, "spi1"), /* CS */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */ > SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */ > SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */ > SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */ > SUNXI_FUNCTION(0x4, "uart3"), /* TX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */ > SUNXI_FUNCTION(0x4, "uart3"), /* RX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */ > SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */ > SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */ > SUNXI_FUNCTION(0x4, "uart4"), /* TX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */ > SUNXI_FUNCTION(0x4, "uart4"), /* RX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), >
On Tue, Jan 14, 2025 at 5:00 PM Andre Przywara <andre.przywara@arm.com> wrote: > Linus, in contrast to what I originally thought, this patch *is* fine, so > feel free to keep it in your tree. > Sorry for the noise! Phew thanks Andre, I would have pulled it out otherwise so it's no big deal, I'm just happy about active maintainers! Yours, Linus Walleij
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c index df90c75fb3c5..b97de80ae2f3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */ SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */ SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */ SUNXI_FUNCTION(0x4, "spi1"), /* CS */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */ SUNXI_FUNCTION(0x4, "uart3"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */ SUNXI_FUNCTION(0x4, "uart3"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */ SUNXI_FUNCTION(0x4, "uart4"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */ SUNXI_FUNCTION(0x4, "uart4"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
lvds, lcd, dsi all shares the same GPIO D bank and lvds0 data 3 lines and lvds1 pins are missed, add them. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> --- drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)