[28/73] tcg: Merge TCG_TARGET_HAS_{add2,sub2}

Message ID	20250102180654.1420056-29-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 28/73] tcg: Merge TCG_TARGET_HAS_{add2,sub2} Date: Thu, 2 Jan 2025 10:06:08 -0800 Message-ID: <20250102180654.1420056-29-richard.henderson@linaro.org> In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Merge _i32 and _i64 opcodes \| expand [00/73] tcg: Merge _i32 and _i64 opcodes [01/73] tcg: Add TCGOp.type [02/73] tcg: Add TCGHelperInfo.out_type [03/73] tcg: Add TCGType argument to tcg_emit_op, tcg_op_insert_* [04/73] tcg: Add TCGType argument to tcg_gen_op* [05/73] tcg: Remove TCGOP_VECL [06/73] tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc [07/73] tcg: Add TCGType argument to tcg_op_supported [08/73] target/arm: Do not test TCG_TARGET_HAS_bitsel_vec [09/73] target/arm: Use tcg_op_supported [10/73] target/tricore: Use tcg_op_supported [11/73] tcg: Add tcg_op_deposit_valid [12/73] target/i386: Remove TCG_TARGET_extract_tl_valid [13/73] target/i386: Use tcg_op_deposit_valid [14/73] target/i386: Use tcg_op_supported [15/73] tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS [16/73] tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc [17/73] tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc [18/73] tcg: Move fallback tcg_can_emit_vec_op out of line [19/73] tcg: Split out tcg-target-has.h and tcg-has.h [20/73] tcg: Split out tcg-target-mo.h [21/73] tcg: Merge TCG_TARGET_HAS_{div,rem,div2} [22/73] tcg: Merge TCG_TARGET_HAS_{andc,orc,nand,nor,eqv,not} [23/73] tcg/mips: Expand bswap unconditionally [24/73] tcg: Merge TCG_TARGET_HAS_bswap* [25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64} [26/73] tcg: Merge TCG_TARGET_HAS_{clz,ctz,ctpop} [27/73] tcg: Merge TCG_TARGET_HAS_{muls2,mulu2,mulsh,muluh} [28/73] tcg: Merge TCG_TARGET_HAS_{add2,sub2} [29/73] tcg: Merge TCG_TARGET_HAS_negsetcond_{i32,i64} [30/73] tcg/i386: Handle all 8-bit extensions for i686 [31/73] tcg/i386: Fold the ext{8, 16, 32}[us] cases into {s}extract [32/73] tcg/aarch64: Provide TCG_TARGET_{s}extract_valid [33/73] tcg/aarch64: Expand extract with offset 0 with andi [34/73] tcg/arm: Add full [US]XT[BH] into {s}extract [35/73] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract [36/73] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract [37/73] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract [38/73] tcg/riscv64: Fold the ext{8, 16, 32}[us] cases into {s}extract [39/73] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 [40/73] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract [41/73] tcg/sparc64: Use SRA, SRL for {s}extract_i64 [42/73] tcg/tci: Provide TCG_TARGET_{s}extract_valid [43/73] tcg/tci: Remove assertions for deposit and extract [44/73] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} [45/73] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} [46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64} [47/73] tcg: Make INDEX_op_extrh_i64_i32 mandatory [48/73] tcg: Remove INDEX_op_ext{8,16,32}{us} [49/73] tcg: Reorg process_op_defs [50/73] tcg: Remove args_ct from TCGOpDef [51/73] tcg: Constify tcg_op_defs [52/73] tcg: Use tcg_op_supported in process_op_defs [53/73] tcg: Use C_NotImplemented in tcg_target_op_def [54/73] tcg: Pass TCGOp to tcg_target_op_def [55/73] tcg: Merge INDEX_op_{ld,st}_{i32_i64} [56/73] tcg: Remove INDEX_op_qemu_st8__i32 [57/73] tcg: Add TCGType argument to tcg_out_op [58/73] tcg/optimize: Remove OptContext.type [59/73] tcg: Remove TCG_OPF_64BIT [60/73] tcg: Change have_vec to has_type in tcg_op_supported [61/73] tcg: Merge INDEX_op_mov_{i32,i64} [62/73] tcg: Merge integer logical operations [63/73] tcg: Merge integer add, sub, neg operations [64/73] tcg: Merge integer add2, sub2 operations [65/73] tcg: Merge integer mul, div operations [66/73] tcg: Merge brcond, setcond, negsetcond, movcond operations [67/73] tcg: Merge extract, sextract operations [68/73] tcg: Merge integer shift operations [69/73] tcg: Merge deposit operations [70/73] tcg: Merge extract2 operations [71/73] tcg: Merge host integer load/store operations [72/73] tcg: Merge bswap operations [73/73] tcg: Merge clz, ctz, ctpop operations

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index fbd759764c..4861b47f56 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -83,8 +83,8 @@ DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32)) DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) -DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32)) -DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32)) +DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2(TCG_TYPE_I32))) +DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2(TCG_TYPE_I32))) DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2(TCG_TYPE_I32))) DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2(TCG_TYPE_I32))) DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh(TCG_TYPE_I32))) @@ -181,8 +181,8 @@ DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz(TCG_TYPE_I64))) DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz(TCG_TYPE_I64))) DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop(TCG_TYPE_I64))) -DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) -DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) +DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2(TCG_TYPE_I64))) +DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2(TCG_TYPE_I64))) DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2(TCG_TYPE_I64))) DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2(TCG_TYPE_I64))) DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh(TCG_TYPE_I64))) diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 53182cca6a..67c61fef9a 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -13,6 +13,7 @@ #define have_lse2 (cpuinfo & CPUINFO_LSE2) /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) 1 #define TCG_TARGET_HAS_ctpop(T) 0 @@ -24,6 +25,7 @@ #define TCG_TARGET_HAS_muluh(T) (T == TCG_TYPE_I64) #define TCG_TARGET_HAS_rem(T) 1 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -42,8 +44,6 @@ #define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 @@ -58,8 +58,6 @@ #define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 /* * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load, diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h index 1352d3c25a..dabb8249f1 100644 --- a/tcg/arm/tcg-target-has.h +++ b/tcg/arm/tcg-target-has.h @@ -24,6 +24,7 @@ extern bool use_neon_instructions; #endif /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) 1 #define TCG_TARGET_HAS_ctpop(T) 0 @@ -35,6 +36,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_muluh(T) 0 #define TCG_TARGET_HAS_rem(T) 0 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h index fc6bd85ba2..b1d28054a9 100644 --- a/tcg/i386/tcg-target-has.h +++ b/tcg/i386/tcg-target-has.h @@ -26,6 +26,7 @@ #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) 1 #define TCG_TARGET_HAS_ctpop(T) have_popcnt @@ -36,6 +37,7 @@ #define TCG_TARGET_HAS_mulsh(T) 0 #define TCG_TARGET_HAS_muluh(T) 0 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) (T >= TCG_TYPE_V64 || have_bmi1) @@ -54,8 +56,6 @@ #define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 #if TCG_TARGET_REG_BITS == 64 /* Keep 32-bit values zero-extended in a register. */ @@ -71,8 +71,6 @@ #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #else #define TCG_TARGET_HAS_qemu_st8_i32 1 diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h index 932acac497..b2fea0f2e1 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -10,6 +10,7 @@ #include "host/cpuinfo.h" /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 0 #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) 1 #define TCG_TARGET_HAS_ctpop(T) 0 @@ -21,6 +22,7 @@ #define TCG_TARGET_HAS_muluh(T) 1 #define TCG_TARGET_HAS_rem(T) 1 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) 0 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -35,8 +37,6 @@ #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -58,8 +58,6 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index f81218178e..a81e54ff8d 100644 --- a/tcg/mips/tcg-target-has.h +++ b/tcg/mips/tcg-target-has.h @@ -39,6 +39,7 @@ extern bool use_mips32r2_instructions; #endif /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) (TCG_TARGET_REG_BITS == 32) #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) use_mips32r2_instructions #define TCG_TARGET_HAS_ctpop(T) 0 @@ -50,6 +51,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh(T) 1 #define TCG_TARGET_HAS_rem(T) 1 #define TCG_TARGET_HAS_rot(T) use_mips32r2_instructions +#define TCG_TARGET_HAS_sub2(T) (TCG_TARGET_REG_BITS == 32) +#define TCG_TARGET_HAS_extract2(T) 0 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 0 @@ -62,11 +65,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_negsetcond_i32 0 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_ext32s_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 0 diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h index 60da23a66a..96d7806ee0 100644 --- a/tcg/ppc/tcg-target-has.h +++ b/tcg/ppc/tcg-target-has.h @@ -17,6 +17,7 @@ #define have_vsx (cpuinfo & CPUINFO_VSX) /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) (T == TCG_TYPE_REG) #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) 1 #define TCG_TARGET_HAS_ctpop(T) have_isa_2_06 @@ -28,6 +29,7 @@ #define TCG_TARGET_HAS_muluh(T) 1 #define TCG_TARGET_HAS_rem(T) 1 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) (T == TCG_TYPE_REG) /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -51,8 +53,6 @@ #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 @@ -65,8 +65,6 @@ #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 #endif #define TCG_TARGET_HAS_qemu_ldst_i128 \ diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index 00eee4cafb..4707bff7a8 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -10,6 +10,7 @@ #include "host/cpuinfo.h" /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_clz(T) (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctpop(T) (cpuinfo & CPUINFO_ZBB) @@ -21,6 +22,7 @@ #define TCG_TARGET_HAS_muluh(T) (T == TCG_TYPE_I64) #define TCG_TARGET_HAS_rem(T) 1 #define TCG_TARGET_HAS_rot(T) (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) (T <= TCG_TYPE_REG && (cpuinfo & CPUINFO_ZBB)) @@ -35,8 +37,6 @@ #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -57,8 +57,6 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 7c0d4708c9..fe3e77107f 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -29,6 +29,7 @@ extern uint64_t s390_facilities[3]; ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) (T == TCG_TYPE_I64) #define TCG_TARGET_HAS_ctpop(T) 1 @@ -39,6 +40,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mulsh(T) 0 #define TCG_TARGET_HAS_muluh(T) 0 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) (T >= TCG_TYPE_V64 || HAVE_FACILITY(MISC_INSN_EXT3)) @@ -57,8 +59,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 1 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 @@ -73,8 +73,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_qemu_ldst_i128 1 diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h index 86b109fc6d..d6376a1b8d 100644 --- a/tcg/sparc64/tcg-target-has.h +++ b/tcg/sparc64/tcg-target-has.h @@ -14,6 +14,7 @@ extern bool use_vis3_instructions; #endif /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) 0 #define TCG_TARGET_HAS_clz(T) 0 #define TCG_TARGET_HAS_ctpop(T) 0 @@ -25,6 +26,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muluh(T) (T == TCG_TYPE_I64 && use_vis3_instructions) #define TCG_TARGET_HAS_rem(T) 0 #define TCG_TARGET_HAS_rot(T) 0 +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -43,8 +45,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_negsetcond_i32 1 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0 @@ -59,8 +59,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h index 199facbe37..56f9725122 100644 --- a/tcg/tcg-has.h +++ b/tcg/tcg-has.h @@ -23,11 +23,6 @@ #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_negsetcond_i64 0 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 -/* Turn some undef macros into true macros. */ -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 #endif #ifndef TCG_TARGET_deposit_i32_valid diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index e0bf8b14bd..27d48670e8 100644 --- a/tcg/tci/tcg-target-has.h +++ b/tcg/tci/tcg-target-has.h @@ -8,6 +8,7 @@ #define TCG_TARGET_HAS_H /* optional integer instructions */ +#define TCG_TARGET_HAS_add2(T) 1 #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_clz(T) 1 #define TCG_TARGET_HAS_ctpop(T) 1 @@ -19,6 +20,7 @@ #define TCG_TARGET_HAS_muluh(T) 0 #define TCG_TARGET_HAS_rem(T) 1 #define TCG_TARGET_HAS_rot(T) 1 +#define TCG_TARGET_HAS_sub2(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -52,10 +54,6 @@ #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 0 -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 #endif /* TCG_TARGET_REG_BITS == 64 */ #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8786aa5903..dde9734615 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1158,7 +1158,7 @@ void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { - if (TCG_TARGET_HAS_add2_i32) { + if (TCG_TARGET_HAS_add2(TCG_TYPE_I32)) { tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh); } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); @@ -1175,7 +1175,7 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { - if (TCG_TARGET_HAS_sub2_i32) { + if (TCG_TARGET_HAS_sub2(TCG_TYPE_I32)) { tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh); } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); @@ -3064,7 +3064,8 @@ void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) { - if (TCG_TARGET_HAS_add2_i64) { + if (TCG_TARGET_REG_BITS == 64 && + TCG_TARGET_HAS_add2(TCG_TYPE_I64)) { tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh); } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); @@ -3082,7 +3083,8 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) { - if (TCG_TARGET_HAS_sub2_i64) { + if (TCG_TARGET_REG_BITS == 64 && + TCG_TARGET_HAS_sub2(TCG_TYPE_I64)) { tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh); } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); diff --git a/tcg/tcg.c b/tcg/tcg.c index 1befe0c4d7..b7ac97efcc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2231,9 +2231,9 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) case INDEX_op_extract2_i32: return TCG_TARGET_HAS_extract2_i32; case INDEX_op_add2_i32: - return TCG_TARGET_HAS_add2_i32; + return TCG_TARGET_HAS_add2(TCG_TYPE_I32); case INDEX_op_sub2_i32: - return TCG_TARGET_HAS_sub2_i32; + return TCG_TARGET_HAS_sub2(TCG_TYPE_I32); case INDEX_op_mulu2_i32: return TCG_TARGET_HAS_mulu2(TCG_TYPE_I32); case INDEX_op_muls2_i32: @@ -2365,9 +2365,9 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) case INDEX_op_ctpop_i64: return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_ctpop(TCG_TYPE_I64); case INDEX_op_add2_i64: - return TCG_TARGET_HAS_add2_i64; + return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_add2(TCG_TYPE_I64); case INDEX_op_sub2_i64: - return TCG_TARGET_HAS_sub2_i64; + return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_sub2(TCG_TYPE_I64); case INDEX_op_mulu2_i64: return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_mulu2(TCG_TYPE_I64); case INDEX_op_muls2_i64: diff --git a/tcg/tci.c b/tcg/tci.c index e71bf82c41..c478988d60 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -657,22 +657,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tb_ptr = ptr; } break; -#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 case INDEX_op_add2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; -#endif -#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; -#endif case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; @@ -778,7 +774,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrr(insn, &r0, &r1, &r2, &r3); muls64(&regs[r0], &regs[r1], regs[r2], regs[r3]); break; -#if TCG_TARGET_HAS_add2_i64 case INDEX_op_add2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = regs[r2] + regs[r4]; @@ -786,8 +781,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = T1; regs[r1] = T2; break; -#endif -#if TCG_TARGET_HAS_add2_i64 case INDEX_op_sub2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = regs[r2] - regs[r4]; @@ -795,7 +788,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = T1; regs[r1] = T2; break; -#endif /* Shift/rotate operations (64 bit). */

[28/73] tcg: Merge TCG_TARGET_HAS_{add2,sub2}

Commit Message

Patch