[52/73] tcg: Use tcg_op_supported in process_op_defs

Message ID	20250102180654.1420056-53-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 52/73] tcg: Use tcg_op_supported in process_op_defs Date: Thu, 2 Jan 2025 10:06:32 -0800 Message-ID: <20250102180654.1420056-53-richard.henderson@linaro.org> In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Merge _i32 and _i64 opcodes \| expand [00/73] tcg: Merge _i32 and _i64 opcodes [01/73] tcg: Add TCGOp.type [02/73] tcg: Add TCGHelperInfo.out_type [03/73] tcg: Add TCGType argument to tcg_emit_op, tcg_op_insert_* [04/73] tcg: Add TCGType argument to tcg_gen_op* [05/73] tcg: Remove TCGOP_VECL [06/73] tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc [07/73] tcg: Add TCGType argument to tcg_op_supported [08/73] target/arm: Do not test TCG_TARGET_HAS_bitsel_vec [09/73] target/arm: Use tcg_op_supported [10/73] target/tricore: Use tcg_op_supported [11/73] tcg: Add tcg_op_deposit_valid [12/73] target/i386: Remove TCG_TARGET_extract_tl_valid [13/73] target/i386: Use tcg_op_deposit_valid [14/73] target/i386: Use tcg_op_supported [15/73] tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS [16/73] tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc [17/73] tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc [18/73] tcg: Move fallback tcg_can_emit_vec_op out of line [19/73] tcg: Split out tcg-target-has.h and tcg-has.h [20/73] tcg: Split out tcg-target-mo.h [21/73] tcg: Merge TCG_TARGET_HAS_{div,rem,div2} [22/73] tcg: Merge TCG_TARGET_HAS_{andc,orc,nand,nor,eqv,not} [23/73] tcg/mips: Expand bswap unconditionally [24/73] tcg: Merge TCG_TARGET_HAS_bswap* [25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64} [26/73] tcg: Merge TCG_TARGET_HAS_{clz,ctz,ctpop} [27/73] tcg: Merge TCG_TARGET_HAS_{muls2,mulu2,mulsh,muluh} [28/73] tcg: Merge TCG_TARGET_HAS_{add2,sub2} [29/73] tcg: Merge TCG_TARGET_HAS_negsetcond_{i32,i64} [30/73] tcg/i386: Handle all 8-bit extensions for i686 [31/73] tcg/i386: Fold the ext{8, 16, 32}[us] cases into {s}extract [32/73] tcg/aarch64: Provide TCG_TARGET_{s}extract_valid [33/73] tcg/aarch64: Expand extract with offset 0 with andi [34/73] tcg/arm: Add full [US]XT[BH] into {s}extract [35/73] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract [36/73] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract [37/73] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract [38/73] tcg/riscv64: Fold the ext{8, 16, 32}[us] cases into {s}extract [39/73] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 [40/73] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract [41/73] tcg/sparc64: Use SRA, SRL for {s}extract_i64 [42/73] tcg/tci: Provide TCG_TARGET_{s}extract_valid [43/73] tcg/tci: Remove assertions for deposit and extract [44/73] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} [45/73] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} [46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64} [47/73] tcg: Make INDEX_op_extrh_i64_i32 mandatory [48/73] tcg: Remove INDEX_op_ext{8,16,32}{us} [49/73] tcg: Reorg process_op_defs [50/73] tcg: Remove args_ct from TCGOpDef [51/73] tcg: Constify tcg_op_defs [52/73] tcg: Use tcg_op_supported in process_op_defs [53/73] tcg: Use C_NotImplemented in tcg_target_op_def [54/73] tcg: Pass TCGOp to tcg_target_op_def [55/73] tcg: Merge INDEX_op_{ld,st}_{i32_i64} [56/73] tcg: Remove INDEX_op_qemu_st8__i32 [57/73] tcg: Add TCGType argument to tcg_out_op [58/73] tcg/optimize: Remove OptContext.type [59/73] tcg: Remove TCG_OPF_64BIT [60/73] tcg: Change have_vec to has_type in tcg_op_supported [61/73] tcg: Merge INDEX_op_mov_{i32,i64} [62/73] tcg: Merge integer logical operations [63/73] tcg: Merge integer add, sub, neg operations [64/73] tcg: Merge integer add2, sub2 operations [65/73] tcg: Merge integer mul, div operations [66/73] tcg: Merge brcond, setcond, negsetcond, movcond operations [67/73] tcg: Merge extract, sextract operations [68/73] tcg: Merge integer shift operations [69/73] tcg: Merge deposit operations [70/73] tcg: Merge extract2 operations [71/73] tcg: Merge host integer load/store operations [72/73] tcg: Merge bswap operations [73/73] tcg: Merge clz, ctz, ctpop operations

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index c0b78aab98..eb64012b62 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -33,20 +33,13 @@ DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) /* variable number of parameters */ DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) -DEF(br, 0, 0, 1, TCG_OPF_BB_END) +DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) -#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0) -#if TCG_TARGET_REG_BITS == 32 -# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT -#else -# define IMPL64 TCG_OPF_64BIT -#endif - -DEF(mb, 0, 0, 1, 0) +DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) -DEF(negsetcond_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_negsetcond(TCG_TYPE_I32))) +DEF(negsetcond_i32, 1, 2, 1, 0) DEF(movcond_i32, 1, 4, 1, 0) /* load/store */ DEF(ld8u_i32, 1, 1, 1, 0) @@ -61,12 +54,12 @@ DEF(st_i32, 0, 2, 1, 0) DEF(add_i32, 1, 2, 0, 0) DEF(sub_i32, 1, 2, 0, 0) DEF(mul_i32, 1, 2, 0, 0) -DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div(TCG_TYPE_I32))) -DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div(TCG_TYPE_I32))) -DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem(TCG_TYPE_I32))) -DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem(TCG_TYPE_I32))) -DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2(TCG_TYPE_I32))) -DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2(TCG_TYPE_I32))) +DEF(div_i32, 1, 2, 0, 0) +DEF(divu_i32, 1, 2, 0, 0) +DEF(rem_i32, 1, 2, 0, 0) +DEF(remu_i32, 1, 2, 0, 0) +DEF(div2_i32, 2, 3, 0, 0) +DEF(divu2_i32, 2, 3, 0, 0) DEF(and_i32, 1, 2, 0, 0) DEF(or_i32, 1, 2, 0, 0) DEF(xor_i32, 1, 2, 0, 0) @@ -74,113 +67,112 @@ DEF(xor_i32, 1, 2, 0, 0) DEF(shl_i32, 1, 2, 0, 0) DEF(shr_i32, 1, 2, 0, 0) DEF(sar_i32, 1, 2, 0, 0) -DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I32))) -DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I32))) +DEF(rotl_i32, 1, 2, 0, 0) +DEF(rotr_i32, 1, 2, 0, 0) DEF(deposit_i32, 1, 2, 2, 0) DEF(extract_i32, 1, 1, 2, 0) DEF(sextract_i32, 1, 1, 2, 0) -DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2(TCG_TYPE_I32))) +DEF(extract2_i32, 1, 2, 1, 0) DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) -DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2(TCG_TYPE_I32))) -DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2(TCG_TYPE_I32))) -DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2(TCG_TYPE_I32))) -DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2(TCG_TYPE_I32))) -DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh(TCG_TYPE_I32))) -DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh(TCG_TYPE_I32))) -DEF(brcond2_i32, 0, 4, 2, - TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32)) -DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) +DEF(add2_i32, 2, 4, 0, 0) +DEF(sub2_i32, 2, 4, 0, 0) +DEF(mulu2_i32, 2, 2, 0, 0) +DEF(muls2_i32, 2, 2, 0, 0) +DEF(muluh_i32, 1, 2, 0, 0) +DEF(mulsh_i32, 1, 2, 0, 0) +DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) +DEF(setcond2_i32, 1, 4, 1, 0) -DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap(TCG_TYPE_I32))) -DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap(TCG_TYPE_I32))) -DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not(TCG_TYPE_I32))) +DEF(bswap16_i32, 1, 1, 1, 0) +DEF(bswap32_i32, 1, 1, 1, 0) +DEF(not_i32, 1, 1, 0, 0) DEF(neg_i32, 1, 1, 0, 0) -DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc(TCG_TYPE_I32))) -DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc(TCG_TYPE_I32))) -DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv(TCG_TYPE_I32))) -DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand(TCG_TYPE_I32))) -DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor(TCG_TYPE_I32))) -DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz(TCG_TYPE_I32))) -DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz(TCG_TYPE_I32))) -DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop(TCG_TYPE_I32))) +DEF(andc_i32, 1, 2, 0, 0) +DEF(orc_i32, 1, 2, 0, 0) +DEF(eqv_i32, 1, 2, 0, 0) +DEF(nand_i32, 1, 2, 0, 0) +DEF(nor_i32, 1, 2, 0, 0) +DEF(clz_i32, 1, 2, 0, 0) +DEF(ctz_i32, 1, 2, 0, 0) +DEF(ctpop_i32, 1, 1, 0, 0) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) -DEF(setcond_i64, 1, 2, 1, IMPL64) -DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond(TCG_TYPE_I64))) -DEF(movcond_i64, 1, 4, 1, IMPL64) +DEF(setcond_i64, 1, 2, 1, TCG_OPF_64BIT) +DEF(negsetcond_i64, 1, 2, 1, TCG_OPF_64BIT) +DEF(movcond_i64, 1, 4, 1, TCG_OPF_64BIT) /* load/store */ -DEF(ld8u_i64, 1, 1, 1, IMPL64) -DEF(ld8s_i64, 1, 1, 1, IMPL64) -DEF(ld16u_i64, 1, 1, 1, IMPL64) -DEF(ld16s_i64, 1, 1, 1, IMPL64) -DEF(ld32u_i64, 1, 1, 1, IMPL64) -DEF(ld32s_i64, 1, 1, 1, IMPL64) -DEF(ld_i64, 1, 1, 1, IMPL64) -DEF(st8_i64, 0, 2, 1, IMPL64) -DEF(st16_i64, 0, 2, 1, IMPL64) -DEF(st32_i64, 0, 2, 1, IMPL64) -DEF(st_i64, 0, 2, 1, IMPL64) +DEF(ld8u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld8s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld16u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld16s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld32u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld32s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(st8_i64, 0, 2, 1, TCG_OPF_64BIT) +DEF(st16_i64, 0, 2, 1, TCG_OPF_64BIT) +DEF(st32_i64, 0, 2, 1, TCG_OPF_64BIT) +DEF(st_i64, 0, 2, 1, TCG_OPF_64BIT) /* arith */ -DEF(add_i64, 1, 2, 0, IMPL64) -DEF(sub_i64, 1, 2, 0, IMPL64) -DEF(mul_i64, 1, 2, 0, IMPL64) -DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div(TCG_TYPE_I64))) -DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div(TCG_TYPE_I64))) -DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem(TCG_TYPE_I64))) -DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem(TCG_TYPE_I64))) -DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2(TCG_TYPE_I64))) -DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2(TCG_TYPE_I64))) -DEF(and_i64, 1, 2, 0, IMPL64) -DEF(or_i64, 1, 2, 0, IMPL64) -DEF(xor_i64, 1, 2, 0, IMPL64) +DEF(add_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(sub_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(mul_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(div_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(divu_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rem_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(remu_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(div2_i64, 2, 3, 0, TCG_OPF_64BIT) +DEF(divu2_i64, 2, 3, 0, TCG_OPF_64BIT) +DEF(and_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(or_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(xor_i64, 1, 2, 0, TCG_OPF_64BIT) /* shifts/rotates */ -DEF(shl_i64, 1, 2, 0, IMPL64) -DEF(shr_i64, 1, 2, 0, IMPL64) -DEF(sar_i64, 1, 2, 0, IMPL64) -DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I64))) -DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I64))) -DEF(deposit_i64, 1, 2, 2, IMPL64) -DEF(extract_i64, 1, 1, 2, IMPL64) -DEF(sextract_i64, 1, 1, 2, IMPL64) -DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2(TCG_TYPE_I64))) +DEF(shl_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(shr_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(sar_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rotl_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rotr_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(deposit_i64, 1, 2, 2, TCG_OPF_64BIT) +DEF(extract_i64, 1, 1, 2, TCG_OPF_64BIT) +DEF(sextract_i64, 1, 1, 2, TCG_OPF_64BIT) +DEF(extract2_i64, 1, 2, 1, TCG_OPF_64BIT) /* size changing ops */ -DEF(ext_i32_i64, 1, 1, 0, IMPL64) -DEF(extu_i32_i64, 1, 1, 0, IMPL64) -DEF(extrl_i64_i32, 1, 1, 0, TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0) -DEF(extrh_i64_i32, 1, 1, 0, TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0) +DEF(ext_i32_i64, 1, 1, 0, TCG_OPF_64BIT) +DEF(extu_i32_i64, 1, 1, 0, TCG_OPF_64BIT) +DEF(extrl_i64_i32, 1, 1, 0, 0) +DEF(extrh_i64_i32, 1, 1, 0, 0) -DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64) -DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap(TCG_TYPE_I64))) -DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap(TCG_TYPE_I64))) -DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap(TCG_TYPE_I64))) -DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not(TCG_TYPE_I64))) -DEF(neg_i64, 1, 1, 0, IMPL64) -DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc(TCG_TYPE_I64))) -DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc(TCG_TYPE_I64))) -DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv(TCG_TYPE_I64))) -DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand(TCG_TYPE_I64))) -DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor(TCG_TYPE_I64))) -DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz(TCG_TYPE_I64))) -DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz(TCG_TYPE_I64))) -DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop(TCG_TYPE_I64))) +DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_64BIT) +DEF(bswap16_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(bswap32_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(bswap64_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(not_i64, 1, 1, 0, TCG_OPF_64BIT) +DEF(neg_i64, 1, 1, 0, TCG_OPF_64BIT) +DEF(andc_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(orc_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(eqv_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(nand_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(nor_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(clz_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(ctz_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(ctpop_i64, 1, 1, 0, TCG_OPF_64BIT) -DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2(TCG_TYPE_I64))) -DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2(TCG_TYPE_I64))) -DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2(TCG_TYPE_I64))) -DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2(TCG_TYPE_I64))) -DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh(TCG_TYPE_I64))) -DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh(TCG_TYPE_I64))) +DEF(add2_i64, 2, 4, 0, TCG_OPF_64BIT) +DEF(sub2_i64, 2, 4, 0, TCG_OPF_64BIT) +DEF(mulu2_i64, 2, 2, 0, TCG_OPF_64BIT) +DEF(muls2_i64, 2, 2, 0, TCG_OPF_64BIT) +DEF(muluh_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(mulsh_i64, 1, 2, 0, TCG_OPF_64BIT) #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) /* There are tcg_ctx->insn_start_words here, not just one. */ DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) -DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) -DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) +DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) +DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) @@ -207,90 +199,79 @@ DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1, /* Only used by i386 to cope with stupid register constraints. */ DEF(qemu_st8_a32_i32, 0, 1 + 1, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | - IMPL(TCG_TARGET_HAS_qemu_st8_i32)) + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | - IMPL(TCG_TARGET_HAS_qemu_st8_i32)) + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) /* Only for 64-bit hosts at the moment. */ DEF(qemu_ld_a32_i128, 2, 1, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | - IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) DEF(qemu_ld_a64_i128, 2, 1, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | - IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) DEF(qemu_st_a32_i128, 0, 3, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | - IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) DEF(qemu_st_a64_i128, 0, 3, 1, - TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | - IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) /* Host vector support. */ -#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) - DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) -DEF(dup_vec, 1, 1, 0, IMPLVEC) -DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) +DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR) +DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR) -DEF(ld_vec, 1, 1, 1, IMPLVEC) -DEF(st_vec, 0, 2, 1, IMPLVEC) -DEF(dupm_vec, 1, 1, 1, IMPLVEC) +DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR) +DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR) +DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR) -DEF(add_vec, 1, 2, 0, IMPLVEC) -DEF(sub_vec, 1, 2, 0, IMPLVEC) -DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) -DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) -DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec)) -DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) -DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) -DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) -DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) -DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) -DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) -DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) -DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) +DEF(add_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(sub_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(mul_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(neg_vec, 1, 1, 0, TCG_OPF_VECTOR) +DEF(abs_vec, 1, 1, 0, TCG_OPF_VECTOR) +DEF(ssadd_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(usadd_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(sssub_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(ussub_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(smin_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(umin_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(smax_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(umax_vec, 1, 2, 0, TCG_OPF_VECTOR) -DEF(and_vec, 1, 2, 0, IMPLVEC) -DEF(or_vec, 1, 2, 0, IMPLVEC) -DEF(xor_vec, 1, 2, 0, IMPLVEC) -DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc(TCG_TYPE_V64))) -DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc(TCG_TYPE_V64))) -DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand(TCG_TYPE_V64))) -DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor(TCG_TYPE_V64))) -DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv(TCG_TYPE_V64))) -DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not(TCG_TYPE_V64))) +DEF(and_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(or_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(xor_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(andc_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(orc_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(nand_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(nor_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(eqv_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(not_vec, 1, 1, 0, TCG_OPF_VECTOR) -DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) -DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) -DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) -DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) +DEF(shli_vec, 1, 1, 1, TCG_OPF_VECTOR) +DEF(shri_vec, 1, 1, 1, TCG_OPF_VECTOR) +DEF(sari_vec, 1, 1, 1, TCG_OPF_VECTOR) +DEF(rotli_vec, 1, 1, 1, TCG_OPF_VECTOR) -DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) -DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) -DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) -DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec)) +DEF(shls_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(shrs_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(sars_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(rotls_vec, 1, 2, 0, TCG_OPF_VECTOR) -DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) -DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) -DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) -DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) -DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) +DEF(shlv_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(shrv_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(sarv_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(rotlv_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(rotrv_vec, 1, 2, 0, TCG_OPF_VECTOR) -DEF(cmp_vec, 1, 2, 1, IMPLVEC) +DEF(cmp_vec, 1, 2, 1, TCG_OPF_VECTOR) -DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) -DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) +DEF(bitsel_vec, 1, 3, 0, TCG_OPF_VECTOR) +DEF(cmpsel_vec, 1, 4, 1, TCG_OPF_VECTOR) DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #include "tcg-target-opc.h.inc" #undef DATA64_ARGS -#undef IMPL -#undef IMPL64 -#undef IMPLVEC #undef DEF diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c index e98b3e5fdd..1ebcd9cb1c 100644 --- a/tcg/tcg-common.c +++ b/tcg/tcg-common.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" -#include "tcg-has.h" const TCGOpDef tcg_op_defs[] = { #define DEF(s, oargs, iargs, cargs, flags) \ diff --git a/tcg/tcg.c b/tcg/tcg.c index 7871e349d4..7ba6c45824 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3327,14 +3327,16 @@ static void process_op_defs(TCGContext *s) const TCGOpDef *def = &tcg_op_defs[op]; const TCGConstraintSet *tdefs; unsigned con_set; - int nb_args; + TCGType type; - nb_args = def->nb_iargs + def->nb_oargs; - if (nb_args == 0) { + if (def->flags & TCG_OPF_NOT_PRESENT) { continue; } - if (def->flags & TCG_OPF_NOT_PRESENT) { + type = (def->flags & TCG_OPF_VECTOR ? TCG_TYPE_V64 + : def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 + : TCG_TYPE_I32); + if (!tcg_op_supported(op, type)) { continue; } @@ -3355,17 +3357,17 @@ static void process_op_defs(TCGContext *s) static const TCGArgConstraint *opcode_args_ct(const TCGOp *op) { - const TCGOpDef *def = &tcg_op_defs[op->opc]; + TCGOpcode opc = op->opc; + const TCGOpDef *def = &tcg_op_defs[opc]; unsigned con_set; - if (def->nb_iargs + def->nb_oargs == 0) { - return NULL; - } if (def->flags & TCG_OPF_NOT_PRESENT) { return empty_cts; } - con_set = tcg_target_op_def(op->opc); + tcg_debug_assert(tcg_op_supported(opc, op->type)); + + con_set = tcg_target_op_def(opc); tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); return all_args_cts[con_set]; } diff --git a/tcg/aarch64/tcg-target-opc.h.inc b/tcg/aarch64/tcg-target-opc.h.inc index bce30accd9..5382315c41 100644 --- a/tcg/aarch64/tcg-target-opc.h.inc +++ b/tcg/aarch64/tcg-target-opc.h.inc @@ -11,5 +11,5 @@ * consider these to be UNSPEC with names. */ -DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) -DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC) +DEF(aa64_sshl_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(aa64_sli_vec, 1, 2, 1, TCG_OPF_VECTOR) diff --git a/tcg/arm/tcg-target-opc.h.inc b/tcg/arm/tcg-target-opc.h.inc index d38af9a808..70394e0282 100644 --- a/tcg/arm/tcg-target-opc.h.inc +++ b/tcg/arm/tcg-target-opc.h.inc @@ -11,6 +11,6 @@ * consider these to be UNSPEC with names. */ -DEF(arm_sli_vec, 1, 2, 1, IMPLVEC) -DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC) -DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC) +DEF(arm_sli_vec, 1, 2, 1, TCG_OPF_VECTOR) +DEF(arm_sshl_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(arm_ushl_vec, 1, 2, 0, TCG_OPF_VECTOR) diff --git a/tcg/i386/tcg-target-opc.h.inc b/tcg/i386/tcg-target-opc.h.inc index 4ffc084bda..8cc0dbaeaf 100644 --- a/tcg/i386/tcg-target-opc.h.inc +++ b/tcg/i386/tcg-target-opc.h.inc @@ -24,14 +24,14 @@ * consider these to be UNSPEC with names. */ -DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC) -DEF(x86_blend_vec, 1, 2, 1, IMPLVEC) -DEF(x86_packss_vec, 1, 2, 0, IMPLVEC) -DEF(x86_packus_vec, 1, 2, 0, IMPLVEC) -DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC) -DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC) -DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC) -DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC) -DEF(x86_vpshldi_vec, 1, 2, 1, IMPLVEC) -DEF(x86_vpshldv_vec, 1, 3, 0, IMPLVEC) -DEF(x86_vpshrdv_vec, 1, 3, 0, IMPLVEC) +DEF(x86_shufps_vec, 1, 2, 1, TCG_OPF_VECTOR) +DEF(x86_blend_vec, 1, 2, 1, TCG_OPF_VECTOR) +DEF(x86_packss_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(x86_packus_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(x86_psrldq_vec, 1, 1, 1, TCG_OPF_VECTOR) +DEF(x86_vperm2i128_vec, 1, 2, 1, TCG_OPF_VECTOR) +DEF(x86_punpckl_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(x86_punpckh_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(x86_vpshldi_vec, 1, 2, 1, TCG_OPF_VECTOR) +DEF(x86_vpshldv_vec, 1, 3, 0, TCG_OPF_VECTOR) +DEF(x86_vpshrdv_vec, 1, 3, 0, TCG_OPF_VECTOR) diff --git a/tcg/ppc/tcg-target-opc.h.inc b/tcg/ppc/tcg-target-opc.h.inc index db514403c3..c3635831b5 100644 --- a/tcg/ppc/tcg-target-opc.h.inc +++ b/tcg/ppc/tcg-target-opc.h.inc @@ -24,9 +24,9 @@ * consider these to be UNSPEC with names. */ -DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC) -DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC) -DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) -DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) -DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) -DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mrgh_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(ppc_mrgl_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(ppc_msum_vec, 1, 3, 0, TCG_OPF_VECTOR) +DEF(ppc_muleu_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(ppc_mulou_vec, 1, 2, 0, TCG_OPF_VECTOR) +DEF(ppc_pkum_vec, 1, 2, 0, TCG_OPF_VECTOR) diff --git a/tcg/s390x/tcg-target-opc.h.inc b/tcg/s390x/tcg-target-opc.h.inc index 0eb2350fb3..61237b39cd 100644 --- a/tcg/s390x/tcg-target-opc.h.inc +++ b/tcg/s390x/tcg-target-opc.h.inc @@ -10,6 +10,6 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ -DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC) -DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC) -DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC) +DEF(s390_vuph_vec, 1, 1, 0, TCG_OPF_VECTOR) +DEF(s390_vupl_vec, 1, 1, 0, TCG_OPF_VECTOR) +DEF(s390_vpks_vec, 1, 2, 0, TCG_OPF_VECTOR)

[52/73] tcg: Use tcg_op_supported in process_op_defs

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Patch