@@ -172,6 +172,8 @@ typedef enum S390Opcode {
RRE_SLBGR = 0xb989,
RRE_XGR = 0xb982,
+ RRFa_ARK = 0xb9f8,
+ RRFa_AGRK = 0xb9e8,
RRFa_MGRK = 0xb9ec,
RRFa_MSRKC = 0xb9fd,
RRFa_MSGRKC = 0xb9ed,
@@ -2255,12 +2257,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tgen_addi(s, type, a0, a1, a2);
- } else if (a0 != a1) {
- tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
- } else if (type == TCG_TYPE_I32) {
+ } else if (type != TCG_TYPE_I32) {
+ tcg_out_insn(s, RRFa, AGRK, a0, a1, a2);
+ } else if (a0 == a1) {
tcg_out_insn(s, RR, AR, a0, a2);
} else {
- tcg_out_insn(s, RRE, AGR, a0, a2);
+ tcg_out_insn(s, RRFa, ARK, a0, a1, a2);
}
break;
Since c68d5b7a6af, we assume the distinct-operands facility, and check for it at startup with HAVE_FACILITY(45). While LA, ARK and AGRK are the same size, the latter are more exactly the operation we wish to perform, and ARK may have a different register rename path through the microcode, ignoring the high 32-bits of the inputs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- Based-on: 20250102180654.1420056-1-richard.henderson@linaro.org ("[PATCH 00/73] tcg: Merge *_i32 and *_i64 opcodes") --- tcg/s390x/tcg-target.c.inc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)