[25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64}

Message ID	20250102180654.1420056-26-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64} Date: Thu, 2 Jan 2025 10:06:05 -0800 Message-ID: <20250102180654.1420056-26-richard.henderson@linaro.org> In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Merge _i32 and _i64 opcodes \| expand [00/73] tcg: Merge _i32 and _i64 opcodes [01/73] tcg: Add TCGOp.type [02/73] tcg: Add TCGHelperInfo.out_type [03/73] tcg: Add TCGType argument to tcg_emit_op, tcg_op_insert_* [04/73] tcg: Add TCGType argument to tcg_gen_op* [05/73] tcg: Remove TCGOP_VECL [06/73] tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc [07/73] tcg: Add TCGType argument to tcg_op_supported [08/73] target/arm: Do not test TCG_TARGET_HAS_bitsel_vec [09/73] target/arm: Use tcg_op_supported [10/73] target/tricore: Use tcg_op_supported [11/73] tcg: Add tcg_op_deposit_valid [12/73] target/i386: Remove TCG_TARGET_extract_tl_valid [13/73] target/i386: Use tcg_op_deposit_valid [14/73] target/i386: Use tcg_op_supported [15/73] tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS [16/73] tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc [17/73] tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc [18/73] tcg: Move fallback tcg_can_emit_vec_op out of line [19/73] tcg: Split out tcg-target-has.h and tcg-has.h [20/73] tcg: Split out tcg-target-mo.h [21/73] tcg: Merge TCG_TARGET_HAS_{div,rem,div2} [22/73] tcg: Merge TCG_TARGET_HAS_{andc,orc,nand,nor,eqv,not} [23/73] tcg/mips: Expand bswap unconditionally [24/73] tcg: Merge TCG_TARGET_HAS_bswap* [25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64} [26/73] tcg: Merge TCG_TARGET_HAS_{clz,ctz,ctpop} [27/73] tcg: Merge TCG_TARGET_HAS_{muls2,mulu2,mulsh,muluh} [28/73] tcg: Merge TCG_TARGET_HAS_{add2,sub2} [29/73] tcg: Merge TCG_TARGET_HAS_negsetcond_{i32,i64} [30/73] tcg/i386: Handle all 8-bit extensions for i686 [31/73] tcg/i386: Fold the ext{8, 16, 32}[us] cases into {s}extract [32/73] tcg/aarch64: Provide TCG_TARGET_{s}extract_valid [33/73] tcg/aarch64: Expand extract with offset 0 with andi [34/73] tcg/arm: Add full [US]XT[BH] into {s}extract [35/73] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract [36/73] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract [37/73] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract [38/73] tcg/riscv64: Fold the ext{8, 16, 32}[us] cases into {s}extract [39/73] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 [40/73] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract [41/73] tcg/sparc64: Use SRA, SRL for {s}extract_i64 [42/73] tcg/tci: Provide TCG_TARGET_{s}extract_valid [43/73] tcg/tci: Remove assertions for deposit and extract [44/73] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} [45/73] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} [46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64} [47/73] tcg: Make INDEX_op_extrh_i64_i32 mandatory [48/73] tcg: Remove INDEX_op_ext{8,16,32}{us} [49/73] tcg: Reorg process_op_defs [50/73] tcg: Remove args_ct from TCGOpDef [51/73] tcg: Constify tcg_op_defs [52/73] tcg: Use tcg_op_supported in process_op_defs [53/73] tcg: Use C_NotImplemented in tcg_target_op_def [54/73] tcg: Pass TCGOp to tcg_target_op_def [55/73] tcg: Merge INDEX_op_{ld,st}_{i32_i64} [56/73] tcg: Remove INDEX_op_qemu_st8__i32 [57/73] tcg: Add TCGType argument to tcg_out_op [58/73] tcg/optimize: Remove OptContext.type [59/73] tcg: Remove TCG_OPF_64BIT [60/73] tcg: Change have_vec to has_type in tcg_op_supported [61/73] tcg: Merge INDEX_op_mov_{i32,i64} [62/73] tcg: Merge integer logical operations [63/73] tcg: Merge integer add, sub, neg operations [64/73] tcg: Merge integer add2, sub2 operations [65/73] tcg: Merge integer mul, div operations [66/73] tcg: Merge brcond, setcond, negsetcond, movcond operations [67/73] tcg: Merge extract, sextract operations [68/73] tcg: Merge integer shift operations [69/73] tcg: Merge deposit operations [70/73] tcg: Merge extract2 operations [71/73] tcg: Merge host integer load/store operations [72/73] tcg: Merge bswap operations [73/73] tcg: Merge clz, ctz, ctpop operations

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index cbc8b358f6..511dd04b39 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -74,8 +74,8 @@ DEF(xor_i32, 1, 2, 0, 0) DEF(shl_i32, 1, 2, 0, 0) DEF(shr_i32, 1, 2, 0, 0) DEF(sar_i32, 1, 2, 0, 0) -DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) -DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) +DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I32))) +DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I32))) DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32)) DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32)) @@ -143,8 +143,8 @@ DEF(xor_i64, 1, 2, 0, IMPL64) DEF(shl_i64, 1, 2, 0, IMPL64) DEF(shr_i64, 1, 2, 0, IMPL64) DEF(sar_i64, 1, 2, 0, IMPL64) -DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) -DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) +DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I64))) +DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I64))) DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64)) DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64)) diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h index 128d1dc7c9..fcf4b68454 100644 --- a/tcg/aarch64/tcg-target-has.h +++ b/tcg/aarch64/tcg-target-has.h @@ -16,6 +16,7 @@ #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 1 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -29,7 +30,6 @@ #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 0 @@ -53,7 +53,6 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctpop_i64 0 diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h index 69579e8fb0..1bc6081e17 100644 --- a/tcg/arm/tcg-target-has.h +++ b/tcg/arm/tcg-target-has.h @@ -27,6 +27,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div(T) use_idiv_instructions #define TCG_TARGET_HAS_rem(T) 0 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -40,7 +41,6 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */ #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions #define TCG_TARGET_HAS_ctpop_i32 0 diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h index fcd10fde95..ba6c9ff71a 100644 --- a/tcg/i386/tcg-target-has.h +++ b/tcg/i386/tcg-target-has.h @@ -28,6 +28,7 @@ /* optional integer instructions */ #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div2(T) 1 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) (T >= TCG_TYPE_V64 || have_bmi1) @@ -37,7 +38,6 @@ #define TCG_TARGET_HAS_not(T) (T <= TCG_TYPE_REG || have_avx512vl) #define TCG_TARGET_HAS_orc(T) (T >= TCG_TYPE_V64 && have_avx512vl) -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -60,7 +60,6 @@ #if TCG_TARGET_REG_BITS == 64 /* Keep 32-bit values zero-extended in a register. */ #define TCG_TARGET_HAS_extr_i64_i32 1 -#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h index 36d3dbc00b..0f15c678ce 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -13,6 +13,7 @@ #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 1 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -23,7 +24,6 @@ #define TCG_TARGET_HAS_orc(T) 1 #define TCG_TARGET_HAS_negsetcond_i32 0 -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 @@ -47,7 +47,6 @@ /* 64-bit operations */ #define TCG_TARGET_HAS_negsetcond_i64 0 -#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index d17d464b8b..14d8609d73 100644 --- a/tcg/mips/tcg-target-has.h +++ b/tcg/mips/tcg-target-has.h @@ -42,6 +42,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 1 +#define TCG_TARGET_HAS_rot(T) use_mips32r2_instructions /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 0 @@ -79,7 +80,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions -#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 @@ -92,7 +92,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions -#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h index 8ddf606d63..68c7ff70c9 100644 --- a/tcg/ppc/tcg-target-has.h +++ b/tcg/ppc/tcg-target-has.h @@ -20,6 +20,7 @@ #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 1 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -33,7 +34,6 @@ #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ #define TCG_TARGET_HAS_ext16u_i32 0 -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_clz_i32 1 @@ -54,7 +54,6 @@ #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0 -#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index 32edc4e484..abc806ce4b 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -13,6 +13,7 @@ #define TCG_TARGET_HAS_bswap(T) (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 1 +#define TCG_TARGET_HAS_rot(T) (cpuinfo & CPUINFO_ZBB) /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) (T <= TCG_TYPE_REG && (cpuinfo & CPUINFO_ZBB)) @@ -23,7 +24,6 @@ #define TCG_TARGET_HAS_orc(T) (T <= TCG_TYPE_REG && (cpuinfo & CPUINFO_ZBB)) #define TCG_TARGET_HAS_negsetcond_i32 1 -#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 @@ -46,7 +46,6 @@ #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_negsetcond_i64 1 -#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index ba83f64e76..543fd146b3 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -31,6 +31,7 @@ extern uint64_t s390_facilities[3]; /* optional integer instructions */ #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div2(T) 1 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) (T >= TCG_TYPE_V64 || HAVE_FACILITY(MISC_INSN_EXT3)) @@ -40,7 +41,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_not(T) (T >= TCG_TYPE_V64 || HAVE_FACILITY(MISC_INSN_EXT3)) #define TCG_TARGET_HAS_orc(T) (T >= TCG_TYPE_V64 ? HAVE_FACILITY(VECTOR_ENH1) : HAVE_FACILITY(MISC_INSN_EXT3)) -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -62,7 +62,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 -#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h index 7816a11c09..a3674cabe6 100644 --- a/tcg/sparc64/tcg-target-has.h +++ b/tcg/sparc64/tcg-target-has.h @@ -17,6 +17,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_bswap(T) 0 #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 0 +#define TCG_TARGET_HAS_rot(T) 0 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -26,7 +27,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_not(T) 1 #define TCG_TARGET_HAS_orc(T) 1 -#define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_ext8s_i32 0 #define TCG_TARGET_HAS_ext16s_i32 0 #define TCG_TARGET_HAS_ext8u_i32 0 @@ -48,7 +48,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0 -#define TCG_TARGET_HAS_rot_i64 0 #define TCG_TARGET_HAS_ext8s_i64 0 #define TCG_TARGET_HAS_ext16s_i64 0 #define TCG_TARGET_HAS_ext32s_i64 1 diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h index 6f04e8cf5a..074c0bcbd2 100644 --- a/tcg/tcg-has.h +++ b/tcg/tcg-has.h @@ -12,7 +12,6 @@ #if TCG_TARGET_REG_BITS == 32 /* Turn some undef macros into false macros. */ #define TCG_TARGET_HAS_extr_i64_i32 0 -#define TCG_TARGET_HAS_rot_i64 0 #define TCG_TARGET_HAS_ext8s_i64 0 #define TCG_TARGET_HAS_ext16s_i64 0 #define TCG_TARGET_HAS_ext32s_i64 0 diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index bf3c454255..28e413d5dc 100644 --- a/tcg/tci/tcg-target-has.h +++ b/tcg/tci/tcg-target-has.h @@ -11,6 +11,7 @@ #define TCG_TARGET_HAS_bswap(T) 1 #define TCG_TARGET_HAS_div(T) 1 #define TCG_TARGET_HAS_rem(T) 1 +#define TCG_TARGET_HAS_rot(T) 1 /* optional integer and vector instructions */ #define TCG_TARGET_HAS_andc(T) 1 @@ -31,7 +32,6 @@ #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 1 -#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 @@ -53,7 +53,6 @@ #define TCG_TARGET_HAS_clz_i64 1 #define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_ctpop_i64 1 -#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 1 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2923a33cf6..8cfaad0ece 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -820,7 +820,7 @@ void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - if (TCG_TARGET_HAS_rot_i32) { + if (TCG_TARGET_HAS_rot(TCG_TYPE_I32)) { tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); } else { TCGv_i32 t0, t1; @@ -842,7 +842,7 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); - } else if (TCG_TARGET_HAS_rot_i32) { + } else if (TCG_TARGET_HAS_rot(TCG_TYPE_I32)) { tcg_gen_rotl_i32(ret, arg1, tcg_constant_i32(arg2)); } else { TCGv_i32 t0, t1; @@ -858,7 +858,7 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - if (TCG_TARGET_HAS_rot_i32) { + if (TCG_TARGET_HAS_rot(TCG_TYPE_I32)) { tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); } else { TCGv_i32 t0, t1; @@ -2580,7 +2580,8 @@ void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_HAS_rot_i64) { + if (TCG_TARGET_REG_BITS == 64 && + TCG_TARGET_HAS_rot(TCG_TYPE_I64)) { tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); } else { TCGv_i64 t0, t1; @@ -2601,7 +2602,8 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); - } else if (TCG_TARGET_HAS_rot_i64) { + } else if (TCG_TARGET_REG_BITS == 64 && + TCG_TARGET_HAS_rot(TCG_TYPE_I64)) { tcg_gen_rotl_i64(ret, arg1, tcg_constant_i64(arg2)); } else { TCGv_i64 t0, t1; @@ -2617,7 +2619,8 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { - if (TCG_TARGET_HAS_rot_i64) { + if (TCG_TARGET_REG_BITS == 64 && + TCG_TARGET_HAS_rot(TCG_TYPE_I64)) { tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); } else { TCGv_i64 t0, t1; diff --git a/tcg/tcg.c b/tcg/tcg.c index d3ede3e6ab..0f3e03b7f5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2221,7 +2221,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) return TCG_TARGET_HAS_div2(TCG_TYPE_I32); case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: - return TCG_TARGET_HAS_rot_i32; + return TCG_TARGET_HAS_rot(TCG_TYPE_I32); case INDEX_op_deposit_i32: return TCG_TARGET_HAS_deposit_i32; case INDEX_op_extract_i32: @@ -2318,7 +2318,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type) return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_div2(TCG_TYPE_I64); case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return TCG_TARGET_HAS_rot_i64; + return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_rot(TCG_TYPE_I64); case INDEX_op_deposit_i64: return TCG_TARGET_HAS_deposit_i64; case INDEX_op_extract_i64: diff --git a/tcg/tci.c b/tcg/tci.c index e2926bce61..54838650b7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -631,7 +631,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); break; -#if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = rol32(regs[r1], regs[r2] & 31); @@ -640,7 +639,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = ror32(regs[r1], regs[r2] & 31); break; -#endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); @@ -833,7 +831,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); break; -#if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = rol64(regs[r1], regs[r2] & 63); @@ -842,7 +839,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = ror64(regs[r1], regs[r2] & 63); break; -#endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);

[25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64}

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Patch