| Message ID | 20250121142341.17001-21-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | cpus: Restrict CPU has_work() handlers to system emulation | expand |
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/riscv/cpu.h | 9 +++++---- > target/riscv/internals.h | 3 --- > target/riscv/cpu.c | 8 +++----- > 3 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 97713681cbe..32e8e064f36 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -552,10 +552,6 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); > uint8_t riscv_cpu_default_priority(int irq); > -uint64_t riscv_cpu_all_pending(CPURISCVState *env); > -int riscv_cpu_mirq_pending(CPURISCVState *env); > -int riscv_cpu_sirq_pending(CPURISCVState *env); > -int riscv_cpu_vsirq_pending(CPURISCVState *env); > bool riscv_cpu_fp_enabled(CPURISCVState *env); > target_ulong riscv_cpu_get_geilen(CPURISCVState *env); > void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); > @@ -576,6 +572,11 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc); > bool riscv_cpu_option_set(const char *optname); > > #ifndef CONFIG_USER_ONLY > +bool riscv_cpu_has_work(CPUState *cs); > +uint64_t riscv_cpu_all_pending(CPURISCVState *env); > +int riscv_cpu_mirq_pending(CPURISCVState *env); > +int riscv_cpu_sirq_pending(CPURISCVState *env); > +int riscv_cpu_vsirq_pending(CPURISCVState *env); > void riscv_cpu_do_interrupt(CPUState *cpu); > void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); > void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > diff --git a/target/riscv/internals.h b/target/riscv/internals.h > index 67291933f84..86def39aec2 100644 > --- a/target/riscv/internals.h > +++ b/target/riscv/internals.h > @@ -142,9 +142,6 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) > } > } > > -/* Our implementation of CPUClass::has_work */ > -bool riscv_cpu_has_work(CPUState *cs); > - Why move the declaration from internals.h to cpu.h? r~
On 24/1/25 18:17, Richard Henderson wrote: > On 1/21/25 06:23, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> target/riscv/cpu.h | 9 +++++---- >> target/riscv/internals.h | 3 --- >> target/riscv/cpu.c | 8 +++----- >> 3 files changed, 8 insertions(+), 12 deletions(-) >> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 97713681cbe..32e8e064f36 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -552,10 +552,6 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, >> GByteArray *buf, int reg); >> int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); >> int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int >> *out_rdzero); >> uint8_t riscv_cpu_default_priority(int irq); >> -uint64_t riscv_cpu_all_pending(CPURISCVState *env); >> -int riscv_cpu_mirq_pending(CPURISCVState *env); >> -int riscv_cpu_sirq_pending(CPURISCVState *env); >> -int riscv_cpu_vsirq_pending(CPURISCVState *env); >> bool riscv_cpu_fp_enabled(CPURISCVState *env); >> target_ulong riscv_cpu_get_geilen(CPURISCVState *env); >> void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); >> @@ -576,6 +572,11 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc); >> bool riscv_cpu_option_set(const char *optname); >> #ifndef CONFIG_USER_ONLY >> +bool riscv_cpu_has_work(CPUState *cs); >> +uint64_t riscv_cpu_all_pending(CPURISCVState *env); >> +int riscv_cpu_mirq_pending(CPURISCVState *env); >> +int riscv_cpu_sirq_pending(CPURISCVState *env); >> +int riscv_cpu_vsirq_pending(CPURISCVState *env); >> void riscv_cpu_do_interrupt(CPUState *cpu); >> void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); >> void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, >> diff --git a/target/riscv/internals.h b/target/riscv/internals.h >> index 67291933f84..86def39aec2 100644 >> --- a/target/riscv/internals.h >> +++ b/target/riscv/internals.h >> @@ -142,9 +142,6 @@ static inline float16 check_nanbox_h(CPURISCVState >> *env, uint64_t f) >> } >> } >> -/* Our implementation of CPUClass::has_work */ >> -bool riscv_cpu_has_work(CPUState *cs); >> - > > Why move the declaration from internals.h to cpu.h? I can't see a compelling reason, so I'll keep it there but add !CONFIG_USER_ONLY guard.
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cbe..32e8e064f36 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -552,10 +552,6 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); @@ -576,6 +572,11 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(const char *optname); #ifndef CONFIG_USER_ONLY +bool riscv_cpu_has_work(CPUState *cs); +uint64_t riscv_cpu_all_pending(CPURISCVState *env); +int riscv_cpu_mirq_pending(CPURISCVState *env); +int riscv_cpu_sirq_pending(CPURISCVState *env); +int riscv_cpu_vsirq_pending(CPURISCVState *env); void riscv_cpu_do_interrupt(CPUState *cpu); void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 67291933f84..86def39aec2 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -142,9 +142,6 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) } } -/* Our implementation of CPUClass::has_work */ -bool riscv_cpu_has_work(CPUState *cs); - /* Zjpm addr masking routine */ static inline target_ulong adjust_addr_body(CPURISCVState *env, target_ulong addr, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2c..4a7e02d9a99 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1010,9 +1010,9 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } +#ifndef CONFIG_USER_ONLY bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; /* @@ -1022,10 +1022,8 @@ bool riscv_cpu_has_work(CPUState *cs) return riscv_cpu_all_pending(env) != 0 || riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE || riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE; -#else - return true; -#endif } +#endif /* !CONFIG_USER_ONLY */ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -2912,6 +2910,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps riscv_sysemu_ops = { + .has_work = riscv_cpu_has_work, .get_phys_page_debug = riscv_cpu_get_phys_page_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, @@ -2933,7 +2932,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc;
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/riscv/cpu.h | 9 +++++---- target/riscv/internals.h | 3 --- target/riscv/cpu.c | 8 +++----- 3 files changed, 8 insertions(+), 12 deletions(-)