diff mbox

[Linaro-uefi,linaro-uefi,v5,37/44] D03/USB: fix ehci interrupt pin number

Message ID 1480652017-31676-38-git-send-email-heyi.guo@linaro.org
State Superseded
Headers show

Commit Message

gary guo Dec. 2, 2016, 4:13 a.m. UTC 
The defination of OHCI and EHCI hardware pins are wrong,
the OHCI pin number is 640, and the EHCI hardware pin number
is 641, correct them.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Kefeng Wang <wangkefeng@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 2 +-
 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl
index afd6b47..7265ac8 100644
--- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl
@@ -23,7 +23,7 @@  Scope(_SB)
     })
 
    Name(_PRS, ResourceTemplate() {
-       Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42}
+       Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} //OHCI: 640, EHCI 641
        })
 
    Name(_DSD, Package () {
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl
index 8429a4b..9132965 100644
--- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl
@@ -34,7 +34,7 @@  Scope(_SB)
                         )
                     Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0")
                     {
-                        0x00000041,
+                        641, //EHCI
                     }
                 })
                 Return (RBUF) /* \_SB_.USB0._CRS.RBUF */