@@ -17,24 +17,34 @@ description:
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g043-cru # RZ/G2UL
- - renesas,r9a07g044-cru # RZ/G2{L,LC}
- - renesas,r9a07g054-cru # RZ/V2L
- - const: renesas,rzg2l-cru
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g043-cru # RZ/G2UL
+ - renesas,r9a07g044-cru # RZ/G2{L,LC}
+ - renesas,r9a07g054-cru # RZ/V2L
+ - const: renesas,rzg2l-cru
+
+ - const: renesas,r9a09g047-cru # RZ/G3E
reg:
maxItems: 1
interrupts:
- maxItems: 3
+ maxItems: 5
interrupt-names:
- items:
- - const: image_conv
- - const: image_conv_err
- - const: axi_mst_err
+ oneOf:
+ - items:
+ - const: image_conv
+ - const: image_conv_err
+ - const: axi_mst_err
+ - items:
+ - const: image_conv
+ - const: axi_mst_err
+ - const: vd_addr_wend
+ - const: sd_addr_wend
+ - const: vsd_addr_wend
clocks:
items:
@@ -120,6 +130,7 @@ allOf:
contains:
enum:
- renesas,r9a07g043-cru
+ - renesas,r9a09g047-cru
then:
properties:
ports:
The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five interrups: - image_conv: image_conv irq - axi_mst_err: AXI master error level irq - vd_addr_wend: Video data AXI master addr 0 write end irq - sd_addr_wend: Statistics data AXI master addr 0 write end irq - vsd_addr_wend: Video statistics data AXI master addr 0 write end irq This IP has only one input port 'port@1' similar to the RZ/G2UL CRU. Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> --- .../bindings/media/renesas,rzg2l-cru.yaml | 33 ++++++++++++------- 1 file changed, 22 insertions(+), 11 deletions(-)