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From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
Date: Mon, 10 Feb 2025 12:52:03 +0000
Subject: [PATCH v2 2/3] arm64: dts: exynos: gs101: align poweroff writes
with downstream
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|
| Series |
gs101 reboot updates (DT)
|
expand
|
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e78dcd506a5c..86741994bb7c 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1401,7 +1401,8 @@ pmu_system_controller: system-controller@17460000 { poweroff: syscon-poweroff { compatible = "syscon-poweroff"; offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ - mask = <0x100>; /* reset value */ + mask = <0x00000100>; + value = <0x0>; }; reboot: syscon-reboot {
For power off, downstream only clears bit 8 and leaves all other bits untouched, whereas this here ends up setting bit 8 and clearing all others, due to how sysconf-poweroff parses the DT. I noticed this discrepancy while debugging some reboot related differences between up- and downstream and it's useful to align the behaviour here. Note: for reboot downstream seems to be incorrectly writing 0x00000002 and not just setting bit 1 (which is the only R/W bit in this register), so we keep that one as-is here. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)