Message ID | 20250219073731.853120-1-sowon.na@samsung.com |
---|---|
State | New |
Headers | show |
Series | [v5,1/1] arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC | expand |
On Wed, 19 Feb 2025 16:37:28 +0900, Sowon Na wrote: > Add UFS Phy for ExynosAutov920 > > Like ExynosAutov9, this also uses fixed-rate clock nodes until clock driver > has been supported. The clock nodes are initialized on bootloader stage > thus we don't need to control them so far. > > Changes from v4: > - Place entry in correct order instead of appending to the end. > > [...] Applied, thanks! [1/1] arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC https://git.kernel.org/krzk/linux/c/5893f538e331609fbea244ed14732291edd6ab22 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index a3fd503c1b21..fc6ac531d597 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -567,6 +567,17 @@ pinctrl_hsi2ufs: pinctrl@16d20000 { interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; }; + ufs_0_phy: phy@16e04000 { + compatible = "samsung,exynosautov920-ufs-phy"; + reg = <0x16e04000 0x4000>; + reg-names = "phy-pma"; + clocks = <&xtcxo>; + clock-names = "ref_clk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + status = "disabled"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>;