@@ -201,8 +201,6 @@ void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
void cpu_m68k_restore_fp_status(CPUM68KState *env);
void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
-uint32_t cpu_m68k_get_fpsr(CPUM68KState *env);
-void cpu_m68k_set_fpsr(CPUM68KState *env, uint32_t val);
/*
* Instead of computing the condition codes after each m68k instruction,
@@ -54,8 +54,6 @@ DEF_HELPER_4(fsdiv, void, env, fp, fp, fp)
DEF_HELPER_4(fddiv, void, env, fp, fp, fp)
DEF_HELPER_4(fsgldiv, void, env, fp, fp, fp)
DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_RWG, void, env, fp, fp)
-DEF_HELPER_2(set_fpsr, void, env, i32)
-DEF_HELPER_1(get_fpsr, i32, env)
DEF_HELPER_FLAGS_2(set_fpcr, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(ftst, TCG_CALL_NO_RWG, void, env, fp)
DEF_HELPER_3(fconst, void, env, fp, i32)
@@ -410,20 +410,11 @@ static const VMStateDescription vmstate_freg = {
}
};
-static int fpu_pre_save(void *opaque)
-{
- M68kCPU *s = opaque;
-
- s->env.fpsr = cpu_m68k_get_fpsr(&s->env);
- return 0;
-}
-
static int fpu_post_load(void *opaque, int version)
{
M68kCPU *s = opaque;
cpu_m68k_set_fpcr(&s->env, s->env.fpcr);
- cpu_m68k_set_fpsr(&s->env, s->env.fpsr);
return 0;
}
@@ -432,7 +423,6 @@ const VMStateDescription vmmstate_fpu = {
.version_id = 1,
.minimum_version_id = 1,
.needed = fpu_needed,
- .pre_save = fpu_pre_save,
.post_load = fpu_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(env.fpcr, M68kCPU),
@@ -164,76 +164,34 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val)
cpu_m68k_set_fpcr(env, val);
}
-/* Convert host exception flags to cpu_m68k form. */
-static int cpu_m68k_exceptbits_from_host(int host_bits)
+static void update_fpsr(CPUM68KState *env, int cc)
{
- int target_bits = 0;
+ uint32_t fpsr = env->fpsr;
+ int flags = get_float_exception_flags(&env->fp_status);
- if (host_bits & float_flag_invalid) {
- target_bits |= FPSR_AEXP_IOP;
- }
- if (host_bits & float_flag_overflow) {
- target_bits |= FPSR_AEXP_OVFL;
- }
- if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) {
- target_bits |= FPSR_AEXP_UNFL;
- }
- if (host_bits & float_flag_divbyzero) {
- target_bits |= FPSR_AEXP_DZ;
- }
- if (host_bits & float_flag_inexact) {
- target_bits |= FPSR_AEXC_INEX;
- }
- return target_bits;
-}
+ fpsr &= ~FPSR_CC_MASK;
+ fpsr |= cc;
-/* Convert cpu_m68k exception flags to target form. */
-static int cpu_m68k_exceptbits_to_host(int target_bits)
-{
- int host_bits = 0;
+ if (flags) {
+ set_float_exception_flags(0, &env->fp_status);
- if (target_bits & FPSR_AEXP_IOP) {
- host_bits |= float_flag_invalid;
+ if (flags & float_flag_invalid) {
+ fpsr |= FPSR_AEXP_IOP;
+ }
+ if (flags & float_flag_overflow) {
+ fpsr |= FPSR_AEXP_OVFL;
+ }
+ if (flags & (float_flag_underflow | float_flag_output_denormal_flushed)) {
+ fpsr |= FPSR_AEXP_UNFL;
+ }
+ if (flags & float_flag_divbyzero) {
+ fpsr |= FPSR_AEXP_DZ;
+ }
+ if (flags & float_flag_inexact) {
+ fpsr |= FPSR_AEXC_INEX;
+ }
}
- if (target_bits & FPSR_AEXP_OVFL) {
- host_bits |= float_flag_overflow;
- }
- if (target_bits & FPSR_AEXP_UNFL) {
- host_bits |= float_flag_underflow;
- }
- if (target_bits & FPSR_AEXP_DZ) {
- host_bits |= float_flag_divbyzero;
- }
- if (target_bits & FPSR_AEXC_INEX) {
- host_bits |= float_flag_inexact;
- }
- return host_bits;
-}
-
-uint32_t cpu_m68k_get_fpsr(CPUM68KState *env)
-{
- int host_flags = get_float_exception_flags(&env->fp_status);
- int target_flags = cpu_m68k_exceptbits_from_host(host_flags);
- int except = (env->fpsr & ~FPSR_AEXC_MASK) | target_flags;
- return except;
-}
-
-uint32_t HELPER(get_fpsr)(CPUM68KState *env)
-{
- return cpu_m68k_get_fpsr(env);
-}
-
-void cpu_m68k_set_fpsr(CPUM68KState *env, uint32_t val)
-{
- env->fpsr = val;
-
- int host_flags = cpu_m68k_exceptbits_to_host((int) env->fpsr);
- set_float_exception_flags(host_flags, &env->fp_status);
-}
-
-void HELPER(set_fpsr)(CPUM68KState *env, uint32_t val)
-{
- cpu_m68k_set_fpsr(env, val);
+ env->fpsr = fpsr;
}
#define PREC_BEGIN(prec) \
@@ -442,12 +400,12 @@ void HELPER(fcmp)(CPUM68KState *env, FPReg *val0, FPReg *val1)
FloatRelation float_compare;
float_compare = floatx80_compare(val1->d, val0->d, &env->fp_status);
- env->fpsr = (env->fpsr & ~FPSR_CC_MASK) | float_comp_to_cc(float_compare);
+ update_fpsr(env, float_comp_to_cc(float_compare));
}
void HELPER(ftst)(CPUM68KState *env, FPReg *val)
{
- uint32_t cc = 0;
+ int cc = 0;
if (floatx80_is_neg(val->d)) {
cc |= FPSR_CC_N;
@@ -460,7 +418,7 @@ void HELPER(ftst)(CPUM68KState *env, FPReg *val)
} else if (floatx80_is_zero(val->d)) {
cc |= FPSR_CC_Z;
}
- env->fpsr = (env->fpsr & ~FPSR_CC_MASK) | cc;
+ update_fpsr(env, cc);
}
void HELPER(fconst)(CPUM68KState *env, FPReg *val, uint32_t offset)
@@ -90,7 +90,7 @@ static int m68k_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
case 8: /* fpcontrol */
return gdb_get_reg32(mem_buf, env->fpcr);
case 9: /* fpstatus */
- return gdb_get_reg32(mem_buf, cpu_m68k_get_fpsr(env));
+ return gdb_get_reg32(mem_buf, env->fpsr);
case 10: /* fpiar, not implemented */
return gdb_get_reg32(mem_buf, 0);
}
@@ -112,7 +112,7 @@ static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
cpu_m68k_set_fpcr(env, ldl_be_p(mem_buf));
return 4;
case 9: /* fpstatus */
- cpu_m68k_set_fpsr(env, ldl_be_p(mem_buf));
+ env->fpsr = ldl_be_p(mem_buf);
return 4;
case 10: /* fpiar, not implemented */
return 4;
@@ -4733,7 +4733,7 @@ static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
tcg_gen_movi_i32(res, 0);
break;
case M68K_FPSR:
- gen_helper_get_fpsr(res, tcg_env);
+ tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpsr));
break;
case M68K_FPCR:
tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpcr));
@@ -4747,7 +4747,7 @@ static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
case M68K_FPIAR:
break;
case M68K_FPSR:
- gen_helper_set_fpsr(tcg_env, val);
+ tcg_gen_st_i32(val, tcg_env, offsetof(CPUM68KState, fpsr));
break;
case M68K_FPCR:
gen_helper_set_fpcr(tcg_env, val);
Proper support for m68k exceptions will require testing the FPCR vs the FPSR for every instruction. As a step, do not keep FPSR bits in fp_status, but copy them back to the FPSR in every instruction. Since most of the FPSR must be updated on every insn, handle this from the existing helper_ftst and helper_fcmp functions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/m68k/cpu.h | 2 - target/m68k/helper.h | 2 - target/m68k/cpu.c | 10 ----- target/m68k/fpu_helper.c | 94 +++++++++++----------------------------- target/m68k/helper.c | 4 +- target/m68k/translate.c | 4 +- 6 files changed, 30 insertions(+), 86 deletions(-)