Message ID | 20250309175207.43828-24-philmd@linaro.org |
---|---|
State | New |
Headers | show
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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ced9a4b19sm44139075e9.29.2025.03.09.10.53.57 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 10:53:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 23/38] target/loongarch: Move has_work() from CPUClass to SysemuCPUOps Date: Sun, 9 Mar 2025 18:51:52 +0100 Message-ID: <20250309175207.43828-24-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250309175207.43828-1-philmd@linaro.org> References: <20250309175207.43828-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
[PULL,01/38] linux-user: Only include 'exec/tb-flush.h' header when necessary
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 49f603149dc..ea1665e2705 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -350,11 +350,9 @@ static void loongarch_restore_state_to_opc(CPUState *cs, } #endif /* CONFIG_TCG */ +#ifndef CONFIG_USER_ONLY static bool loongarch_cpu_has_work(CPUState *cs) { -#ifdef CONFIG_USER_ONLY - return true; -#else bool has_work = false; if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && @@ -363,8 +361,8 @@ static bool loongarch_cpu_has_work(CPUState *cs) } return has_work; -#endif } +#endif /* !CONFIG_USER_ONLY */ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -885,6 +883,7 @@ static const TCGCPUOps loongarch_tcg_ops = { #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps loongarch_sysemu_ops = { + .has_work = loongarch_cpu_has_work, .write_elf64_note = loongarch_cpu_write_elf64_note, .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, }; @@ -920,7 +919,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) &lacc->parent_phases); cc->class_by_name = loongarch_cpu_class_by_name; - cc->has_work = loongarch_cpu_has_work; cc->mmu_index = loongarch_cpu_mmu_index; cc->dump_state = loongarch_cpu_dump_state; cc->set_pc = loongarch_cpu_set_pc;