| Message ID | 20250317-sc7280-mmc-ufs-clocks-v1-2-38e05c16511b@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | clk/qcom: fix UFS and MMC clock enable errors | expand |
On 17/03/2025 17:15, Caleb Connolly wrote: > These are all usually enabled, hence we don't (yet) bother configuring > their RCG src clocks. > > Add them to remove the errors about missing clocks when the UFS and MMC > drivers probe. > > Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> > --- > drivers/clk/qcom/clock-sc7280.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c > index 8691f08109b39639d8a5defe75161049399bf682..9aff8a847ad1bd59b7ec7246f5719e4d7c32ec65 100644 > --- a/drivers/clk/qcom/clock-sc7280.c > +++ b/drivers/clk/qcom/clock-sc7280.c > @@ -106,8 +106,19 @@ static const struct gate_clk sc7280_clks[] = { > GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)), > GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)), > GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)), > GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)), > + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), > + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), > + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), > + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), > + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), > + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), > + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, BIT(0)), > + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, BIT(0)), > + GATE_CLK(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0)), > + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)), > + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), > }; > > static int sc7280_enable(struct clk *clk) > { > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 8691f08109b39639d8a5defe75161049399bf682..9aff8a847ad1bd59b7ec7246f5719e4d7c32ec65 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -106,8 +106,19 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)), GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, BIT(0)), + GATE_CLK(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), }; static int sc7280_enable(struct clk *clk) {
These are all usually enabled, hence we don't (yet) bother configuring their RCG src clocks. Add them to remove the errors about missing clocks when the UFS and MMC drivers probe. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> --- drivers/clk/qcom/clock-sc7280.c | 11 +++++++++++ 1 file changed, 11 insertions(+)