diff mbox series

[PATCH-for-10.1,v2,38/43] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'

Message ID 20250402212319.58349-2-philmd@linaro.org
State New
Headers show
Series tcg: philmd's queue | expand

Commit Message

Philippe Mathieu-Daudé April 2, 2025, 9:23 p.m. UTC 
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 accel/tcg/backend-ldst.h    | 41 +++++++++++++++++++++++++++++++++++++
 accel/tcg/internal-common.h | 27 ++++++++++++++++++++++++
 accel/tcg/internal-target.h | 28 -------------------------
 accel/tcg/cputlb.c          |  1 +
 accel/tcg/user-exec.c       |  1 +
 5 files changed, 70 insertions(+), 28 deletions(-)
 create mode 100644 accel/tcg/backend-ldst.h

Comments

Richard Henderson April 3, 2025, 2:54 p.m. UTC | #1 
On 4/2/25 14:23, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   accel/tcg/backend-ldst.h    | 41 +++++++++++++++++++++++++++++++++++++
>   accel/tcg/internal-common.h | 27 ++++++++++++++++++++++++
>   accel/tcg/internal-target.h | 28 -------------------------
>   accel/tcg/cputlb.c          |  1 +
>   accel/tcg/user-exec.c       |  1 +
>   5 files changed, 70 insertions(+), 28 deletions(-)
>   create mode 100644 accel/tcg/backend-ldst.h
> 
> diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h
> new file mode 100644
> index 00000000000..9c3a407a5af
> --- /dev/null
> +++ b/accel/tcg/backend-ldst.h
> @@ -0,0 +1,41 @@
> +/*
> + * Internal memory barrier helpers for QEMU (target agnostic)
> + *
> + *  Copyright (c) 2003 Fabrice Bellard
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#ifndef ACCEL_TCG_BACKEND_LDST_H
> +#define ACCEL_TCG_BACKEND_LDST_H
> +
> +#include "tcg-target-mo.h"
> +
> +/**
> + * tcg_req_mo:
> + * @guest_mo: Guest default memory order
> + * @type: TCGBar
> + *
> + * Filter @type to the barrier that is required for the guest
> + * memory ordering vs the host memory ordering.  A non-zero
> + * result indicates that some barrier is required.
> + */
> +#define tcg_req_mo(guest_mo, type) \
> +    ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
> +
> +/**
> + * cpu_req_mo:
> + * @cpu: CPUState
> + * @type: TCGBar
> + *
> + * If tcg_req_mo indicates a barrier for @type is required
> + * for the guest memory model, issue a host memory barrier.
> + */
> +#define cpu_req_mo(cpu, type)     \
> +    do {                          \
> +        if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
> +            smp_mb();             \
> +        }                         \
> +    } while (0)
> +
> +#endif
> diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
> index 2f00560d102..829ae9389d2 100644
> --- a/accel/tcg/internal-common.h
> +++ b/accel/tcg/internal-common.h
> @@ -108,4 +108,31 @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
>       return get_page_addr_code_hostp(env, addr, NULL);
>   }
>   
> +/**
> + * tcg_req_mo:
> + * @guest_mo: Guest default memory order
> + * @type: TCGBar
> + *
> + * Filter @type to the barrier that is required for the guest
> + * memory ordering vs the host memory ordering.  A non-zero
> + * result indicates that some barrier is required.
> + */
> +#define tcg_req_mo(guest_mo, type) \
> +    ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
> +
> +/**
> + * cpu_req_mo:
> + * @cpu: CPUState
> + * @type: TCGBar
> + *
> + * If tcg_req_mo indicates a barrier for @type is required
> + * for the guest memory model, issue a host memory barrier.
> + */
> +#define cpu_req_mo(cpu, type)     \
> +    do {                          \
> +        if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
> +            smp_mb();             \
> +        }                         \
> +    } while (0)
> +
>   #endif

I assume you meant to remove this from here in v2.


r~

> diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
> index f5a3fd7e402..9a9cef31406 100644
> --- a/accel/tcg/internal-target.h
> +++ b/accel/tcg/internal-target.h
> @@ -13,7 +13,6 @@
>   #include "exec/exec-all.h"
>   #include "exec/translation-block.h"
>   #include "tb-internal.h"
> -#include "tcg-target-mo.h"
>   #include "exec/mmap-lock.h"
>   
>   /*
> @@ -44,31 +43,4 @@ void page_table_config_init(void);
>   G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
>   #endif /* CONFIG_USER_ONLY */
>   
> -/**
> - * tcg_req_mo:
> - * @guest_mo: Guest default memory order
> - * @type: TCGBar
> - *
> - * Filter @type to the barrier that is required for the guest
> - * memory ordering vs the host memory ordering.  A non-zero
> - * result indicates that some barrier is required.
> - */
> -#define tcg_req_mo(guest_mo, type) \
> -    ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
> -
> -/**
> - * cpu_req_mo:
> - * @cpu: CPUState
> - * @type: TCGBar
> - *
> - * If tcg_req_mo indicates a barrier for @type is required
> - * for the guest memory model, issue a host memory barrier.
> - */
> -#define cpu_req_mo(cpu, type)     \
> -    do {                          \
> -        if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
> -            smp_mb();             \
> -        }                         \
> -    } while (0)
> -
>   #endif /* ACCEL_TCG_INTERNAL_H */
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 35b1ff03a51..d9fb68d7198 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -48,6 +48,7 @@
>   #include "qemu/plugin-memory.h"
>   #endif
>   #include "tcg/tcg-ldst.h"
> +#include "backend-ldst.h"
>   
>   
>   /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 3f4d6824460..5eef8e7f186 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -37,6 +37,7 @@
>   #include "qemu/int128.h"
>   #include "trace.h"
>   #include "tcg/tcg-ldst.h"
> +#include "backend-ldst.h"
>   #include "internal-common.h"
>   #include "internal-target.h"
>   #include "tb-internal.h"
diff mbox series

Patch

diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h
new file mode 100644
index 00000000000..9c3a407a5af
--- /dev/null
+++ b/accel/tcg/backend-ldst.h
@@ -0,0 +1,41 @@ 
+/*
+ * Internal memory barrier helpers for QEMU (target agnostic)
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef ACCEL_TCG_BACKEND_LDST_H
+#define ACCEL_TCG_BACKEND_LDST_H
+
+#include "tcg-target-mo.h"
+
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering.  A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+    ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type)     \
+    do {                          \
+        if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+            smp_mb();             \
+        }                         \
+    } while (0)
+
+#endif
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index 2f00560d102..829ae9389d2 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -108,4 +108,31 @@  static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
     return get_page_addr_code_hostp(env, addr, NULL);
 }
 
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering.  A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+    ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type)     \
+    do {                          \
+        if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+            smp_mb();             \
+        }                         \
+    } while (0)
+
 #endif
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index f5a3fd7e402..9a9cef31406 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -13,7 +13,6 @@ 
 #include "exec/exec-all.h"
 #include "exec/translation-block.h"
 #include "tb-internal.h"
-#include "tcg-target-mo.h"
 #include "exec/mmap-lock.h"
 
 /*
@@ -44,31 +43,4 @@  void page_table_config_init(void);
 G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
 #endif /* CONFIG_USER_ONLY */
 
-/**
- * tcg_req_mo:
- * @guest_mo: Guest default memory order
- * @type: TCGBar
- *
- * Filter @type to the barrier that is required for the guest
- * memory ordering vs the host memory ordering.  A non-zero
- * result indicates that some barrier is required.
- */
-#define tcg_req_mo(guest_mo, type) \
-    ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
-
-/**
- * cpu_req_mo:
- * @cpu: CPUState
- * @type: TCGBar
- *
- * If tcg_req_mo indicates a barrier for @type is required
- * for the guest memory model, issue a host memory barrier.
- */
-#define cpu_req_mo(cpu, type)     \
-    do {                          \
-        if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
-            smp_mb();             \
-        }                         \
-    } while (0)
-
 #endif /* ACCEL_TCG_INTERNAL_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 35b1ff03a51..d9fb68d7198 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -48,6 +48,7 @@ 
 #include "qemu/plugin-memory.h"
 #endif
 #include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
 
 
 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 3f4d6824460..5eef8e7f186 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -37,6 +37,7 @@ 
 #include "qemu/int128.h"
 #include "trace.h"
 #include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
 #include "internal-common.h"
 #include "internal-target.h"
 #include "tb-internal.h"