| Message ID | 20250507031559.4085159-6-quic_ziyuzhan@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | pci: qcom: Add QCS615 PCIe support | expand |
On Wed, May 07, 2025 at 11:15:59AM GMT, Ziyue Zhang wrote: > Add the compatible and the driver data for QCS615 PCIe controller. > There is only one controller instance found on this platform, which > is capable of up to 8.0GT/s. > The version of the controller is 1.38.0 which is compatible with 1.9.0 > config. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index dc98ae63362d..0ed934b0d1be 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1862,6 +1862,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, > + { .compatible = "qcom,qcs615-pcie", .data = &cfg_1_9_0 }, Why? It's compatible with other entries, so why adding redundant entry here? Best regards, Krzysztof
On 5/7/2025 1:18 PM, Krzysztof Kozlowski wrote: > On Wed, May 07, 2025 at 11:15:59AM GMT, Ziyue Zhang wrote: >> Add the compatible and the driver data for QCS615 PCIe controller. >> There is only one controller instance found on this platform, which >> is capable of up to 8.0GT/s. >> The version of the controller is 1.38.0 which is compatible with 1.9.0 >> config. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index dc98ae63362d..0ed934b0d1be 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1862,6 +1862,7 @@ static const struct of_device_id qcom_pcie_match[] = { >> { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, >> { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, >> { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, >> + { .compatible = "qcom,qcs615-pcie", .data = &cfg_1_9_0 }, > Why? It's compatible with other entries, so why adding redundant entry > here? > > Best regards, > Krzysztof Hi Krzysztof If I use the compatible entry for qcs615 in the driver, do I need to add qcom,qcs615-pcie to qcom,pcie-sm8550.yaml, or should I create a new YAML file specifically for qcs615-pcie? Given that the PCIe cores on qcs615 and sm8550 require different clocks, is it acceptable to combine them in qcom,pcie-sm8550.yaml? BRs Ziyue
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index dc98ae63362d..0ed934b0d1be 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1862,6 +1862,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, + { .compatible = "qcom,qcs615-pcie", .data = &cfg_1_9_0 }, { } };