| Message ID | 20250508081514.3227956-3-quic_wenbyao@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: x1e80100-qcp: Add power supply and sideband signals for PCIe RC | expand |
On 5/8/25 10:15 AM, Wenbin Yao wrote: > From: Qiang Yu <quic_qianyu@quicinc.com> > > Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot > voltage rails can be described under this node in the board's dts. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 46b79fce9..430f9d567 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3287,6 +3287,17 @@ opp-128000000 { > opp-peak-kBps = <15753000 1>; > }; > }; > + > + pcie3port: pcie@0 { > + device_type = "pci"; > + compatible = "pciclass,0604"; > + reg = <0x0 0x0 0x0 0x0 0x0>; > + bus-range = <0x01 0xff>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; If you end up setting a v(n+1), please rename the label to 'pcie3_port' Konrad
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce9..430f9d567 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3287,6 +3287,17 @@ opp-128000000 { opp-peak-kBps = <15753000 1>; }; }; + + pcie3port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 {