| Message ID | CABXYE2XBaxNvZmWYAJ=0wGMzX0k0+2w=ODsLh57C_VFVqwW-Wg@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
Hi Jim, > The vector mul instruction is doing a widening multiply, but isn't > supposed to. mull does a widening multiply, mul does a regular > multiply. > > The testcase works with the patch, and fails without the patch. GCC C > testsuite failures drop from 2538 to 2473. Approved - please apply. Also - would you be interested in becoming a maintainer for the AArch64 sim ? I certainly think that it would be good idea, and I think that Mike would probably be onboard with the idea too ... Cheers Nick
On Tue, Jan 3, 2017 at 6:35 AM, Nick Clifton <nickc@redhat.com> wrote: > Also - would you be interested in becoming a maintainer for the AArch64 sim ? > I certainly think that it would be good idea, and I think that Mike would > probably be onboard with the idea too ... Yes, I am willing to become a maintainer or co-maintainer for the AArch64 sim. I'll have to start reading gdb-patches again to look for aarch64 sim related messages, but I doubt that there are many relevant ones. Jim
Hi Mike, >> On Tue, Jan 3, 2017 at 6:35 AM, Nick Clifton <nickc@redhat.com> wrote: >> Also - would you be interested in becoming a maintainer for the AArch64 sim ? > On 05/01/17 00:13, Jim Wilson wrote: > Yes, I am willing to become a maintainer or co-maintainer for the > AArch64 sim. How about it Mike - can we add Jim as an AArch64 sim maintainer ? Cheers Nick
On 05 Jan 2017 10:09, Nick Clifton wrote: > >> On Tue, Jan 3, 2017 at 6:35 AM, Nick Clifton <nickc@redhat.com> wrote: > >> Also - would you be interested in becoming a maintainer for the AArch64 sim ? > > > On 05/01/17 00:13, Jim Wilson wrote: > > Yes, I am willing to become a maintainer or co-maintainer for the > > AArch64 sim. > > How about it Mike - can we add Jim as an AArch64 sim maintainer ? np -- Jim is clearly doing great work feel free to update the MAINTAINERS file! -mike
Hi Mike, > np -- Jim is clearly doing great work > > feel free to update the MAINTAINERS file! Great - thanks Mike, and welcome on board Jim. Cheers Nick
2016-12-23 Jim Wilson <jim.wilson@linaro.org> sim/aarch64/ * simulator.c (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. sim/testsuite/sim/aarch64/ * mul.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index be3d6c7..9da12d3 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3724,15 +3724,15 @@ do_vec_mul (sim_cpu *cpu) switch (INSTR (23, 22)) { case 0: - DO_VEC_WIDENING_MUL (full ? 16 : 8, uint16_t, u8, u16); + DO_VEC_WIDENING_MUL (full ? 16 : 8, uint8_t, u8, u8); return; case 1: - DO_VEC_WIDENING_MUL (full ? 8 : 4, uint32_t, u16, u32); + DO_VEC_WIDENING_MUL (full ? 8 : 4, uint16_t, u16, u16); return; case 2: - DO_VEC_WIDENING_MUL (full ? 4 : 2, uint64_t, u32, u64); + DO_VEC_WIDENING_MUL (full ? 4 : 2, uint32_t, u32, u32); return; case 3: diff --git a/sim/testsuite/sim/aarch64/mul.s b/sim/testsuite/sim/aarch64/mul.s new file mode 100644 index 0000000..783dba7 --- /dev/null +++ b/sim/testsuite/sim/aarch64/mul.s @@ -0,0 +1,99 @@ +# mach: aarch64 + +# Check the non-widening multiply vector instruction: mul. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0x10090401 + .word 0x40312419 +m16b: + .word 0x10090401 + .word 0x40312419 + .word 0x90796451 + .word 0x00e1c4a9 +m4h: + .word 0x18090401 + .word 0x70313c19 +m8h: + .word 0x18090401 + .word 0x70313c19 + .word 0x0879b451 + .word 0xe0e16ca9 +m2s: + .word 0x140a0401 + .word 0xa46a3c19 +m4s: + .word 0x140a0401 + .word 0xa46a3c19 + .word 0xb52ab451 + .word 0x464b6ca9 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + mul v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x0, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + mul v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x0, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + mul v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x0, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + mul v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x0, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + mul v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x0, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + mul v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x0, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail