| Message ID | 20250526-b4-k1-dwc3-v3-v4-2-63e4e525e5cb@whut.edu.cn |
|---|---|
| State | New |
| Headers | show |
| Series | Add SpacemiT K1 USB3.0 host controller support | expand |
On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote: > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus > (MBUS) that is not their immediate parent in the device tree. This bus > uses a different address mapping than the CPU. > > To express this topology properly, devices are expected to use the > interconnects with name "dma-mem" to reference the MBUS controller. I don't get it, sorry. Devices performing DMA through foo-bar should use dmas property for foo-bar DMA controller. Interconnects is not for that. > > Signed-off-by: Ze Huang <huangze@whut.edu.cn> > --- > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SpacemiT Memory Bus controller > + > +maintainers: > + - Ze Huang <huangze9015@gmail.com> > + > +description: | > + On the SpacemiT K1 SoC, some devices do not perform DMA through their > + immediate parent node in the device tree. Instead, they access memory > + through a separate memory bus (MBUS) that uses a different address > + mapping from the CPU. > + > + To correctly describe the DMA path, such devices must reference the MBUS > + controller through an interconnect with the reserved name "dma-mem". > + > +properties: > + compatible: > + const: spacemit,k1-mbus > + > + reg: > + maxItems: 1 > + > + dma-ranges: > + maxItems: 1 > + > + "#address-cells": true > + > + "#size-cells": true No improvements. > + > + "#interconnect-cells": > + const: 0 This is not a interconnect provider, but DMA controller, according to youro description. > + > +required: > + - compatible > + - reg > + - dma-ranges > + - "#interconnect-cells" > + > +additionalProperties: false > + > +examples: > + - | > + dram-controller@0 { Either dma-controller or memory-controller, decide what is this. > + compatible = "spacemit,k1-mbus"; > + reg = <0x00000000 0x80000000>; > + dma-ranges = <0x00000000 0x00000000 0x80000000>; > + #address-cells = <1>; > + #size-cells = <1>; Nothing improved. > + #interconnect-cells = <0>; > + }; > > -- > 2.49.0 >
On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote: > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus > (MBUS) that is not their immediate parent in the device tree. This bus > uses a different address mapping than the CPU. > > To express this topology properly, devices are expected to use the > interconnects with name "dma-mem" to reference the MBUS controller. > > Signed-off-by: Ze Huang <huangze@whut.edu.cn> > --- > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml Memory bus controllers go to /memory-controllers/ directory. Best regards, Krzysztof
On Tue, May 27, 2025 at 08:54:42AM +0200, Krzysztof Kozlowski wrote: > On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote: > > Some devices on the SpacemiT K1 SoC perform DMA through a memory bus > > (MBUS) that is not their immediate parent in the device tree. This bus > > uses a different address mapping than the CPU. > > > > To express this topology properly, devices are expected to use the > > interconnects with name "dma-mem" to reference the MBUS controller. > > > > Signed-off-by: Ze Huang <huangze@whut.edu.cn> > > --- > > .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml > > Memory bus controllers go to /memory-controllers/ directory. > > Best regards, > Krzysztof OK
On 5/28/25 12:25 AM, Rob Herring wrote: > On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote: >> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote: >>> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote: >>>> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus >>>> (MBUS) that is not their immediate parent in the device tree. This bus >>>> uses a different address mapping than the CPU. >>>> >>>> To express this topology properly, devices are expected to use the >>>> interconnects with name "dma-mem" to reference the MBUS controller. >>> I don't get it, sorry. Devices performing DMA through foo-bar should use >>> dmas property for foo-bar DMA controller. Interconnects is not for that. >>> >> Hi Krzysztof, >> >> Sorry for not clarifying this earlier - let me provide some context. >> >> The purpose of this node is to describe the address translation used for DMA >> device to memory transactions. I’m using the "interconnects" property with the >> reserved name "dma-mem" [1] in consumer devices to express this relationship. >> The actual translation is handled by the `of_translate_dma_address()` [2]. >> This support was introduced in the series linked in [3]. >> >> This setup is similar to what we see on platforms like Allwinner sun5i, >> sun8i-r40, and NVIDIA Tegra. [4][5] >> >> I considered reusing the existing Allwinner MBUS driver and bindings. >> However, the Allwinner MBUS includes additional functionality such as >> bandwidth monitoring and frequency control - features that are either >> absent or undocumented on the SpacemiT K1 SoC. > The interconnect binding is for when you have those software controls. > If you only have address translation, then 'dma-ranges' in a parent node > is all you need. > > Rob Different devices on the SoC may have distinct DMA address translations. A common dma-ranges in the parent node may not represent this accurately.
On Tue, May 27, 2025 at 11:42 AM Ze Huang <huangze@whut.edu.cn> wrote: > > On 5/28/25 12:25 AM, Rob Herring wrote: > > On Tue, May 27, 2025 at 07:13:05PM +0800, Ze Huang wrote: > >> On Tue, May 27, 2025 at 08:51:19AM +0200, Krzysztof Kozlowski wrote: > >>> On Mon, May 26, 2025 at 10:40:18PM GMT, Ze Huang wrote: > >>>> Some devices on the SpacemiT K1 SoC perform DMA through a memory bus > >>>> (MBUS) that is not their immediate parent in the device tree. This bus > >>>> uses a different address mapping than the CPU. > >>>> > >>>> To express this topology properly, devices are expected to use the > >>>> interconnects with name "dma-mem" to reference the MBUS controller. > >>> I don't get it, sorry. Devices performing DMA through foo-bar should use > >>> dmas property for foo-bar DMA controller. Interconnects is not for that. > >>> > >> Hi Krzysztof, > >> > >> Sorry for not clarifying this earlier - let me provide some context. > >> > >> The purpose of this node is to describe the address translation used for DMA > >> device to memory transactions. I’m using the "interconnects" property with the > >> reserved name "dma-mem" [1] in consumer devices to express this relationship. > >> The actual translation is handled by the `of_translate_dma_address()` [2]. > >> This support was introduced in the series linked in [3]. > >> > >> This setup is similar to what we see on platforms like Allwinner sun5i, > >> sun8i-r40, and NVIDIA Tegra. [4][5] > >> > >> I considered reusing the existing Allwinner MBUS driver and bindings. > >> However, the Allwinner MBUS includes additional functionality such as > >> bandwidth monitoring and frequency control - features that are either > >> absent or undocumented on the SpacemiT K1 SoC. > > The interconnect binding is for when you have those software controls. > > If you only have address translation, then 'dma-ranges' in a parent node > > is all you need. > > > > Rob > > Different devices on the SoC may have distinct DMA address translations. > A common dma-ranges in the parent node may not represent this accurately. That is solved with different parent bus nodes which would be a more accurate representation of the h/w. If the address translation is different then, the devices have to be on different buses. You can use interconnect binding, but you need to accurately describe the interconnect provider. Rob
diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml new file mode 100644 index 0000000000000000000000000000000000000000..533cf99dff689cf55a159118c32a676054294ffa --- /dev/null +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-mbus.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-mbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT Memory Bus controller + +maintainers: + - Ze Huang <huangze9015@gmail.com> + +description: | + On the SpacemiT K1 SoC, some devices do not perform DMA through their + immediate parent node in the device tree. Instead, they access memory + through a separate memory bus (MBUS) that uses a different address + mapping from the CPU. + + To correctly describe the DMA path, such devices must reference the MBUS + controller through an interconnect with the reserved name "dma-mem". + +properties: + compatible: + const: spacemit,k1-mbus + + reg: + maxItems: 1 + + dma-ranges: + maxItems: 1 + + "#address-cells": true + + "#size-cells": true + + "#interconnect-cells": + const: 0 + +required: + - compatible + - reg + - dma-ranges + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + dram-controller@0 { + compatible = "spacemit,k1-mbus"; + reg = <0x00000000 0x80000000>; + dma-ranges = <0x00000000 0x00000000 0x80000000>; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <0>; + };
Some devices on the SpacemiT K1 SoC perform DMA through a memory bus (MBUS) that is not their immediate parent in the device tree. This bus uses a different address mapping than the CPU. To express this topology properly, devices are expected to use the interconnects with name "dma-mem" to reference the MBUS controller. Signed-off-by: Ze Huang <huangze@whut.edu.cn> --- .../bindings/soc/spacemit/spacemit,k1-mbus.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+)