diff mbox series

[v1,1/1] arm64: dts: exynos990: Add CMU_HSI1 node

Message ID 20250528105821.158140-2-umer.uddin@mentallysanemainliners.org
State New
Headers show
Series Enable CMU_HSI1 for Exynos990 | expand

Commit Message

Umer Uddin May 28, 2025, 10:58 a.m. UTC 
CMU_HSI1 is a new clock controller that provides clocks for the
DesignWare MMC Controller, PCIE subsystem and UFS subsystem.

Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org>
---
 arch/arm64/boot/dts/exynos/exynos990.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi
index dd7f99f51..4ab6e35f0 100644
--- a/arch/arm64/boot/dts/exynos/exynos990.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi
@@ -254,6 +254,25 @@  cmu_hsi0: clock-controller@10a00000 {
 				      "dpgtc";
 		};
 
+		cmu_hsi1: clock-controller@13000000 {
+			compatible = "samsung,exynos990-cmu-hsi1";
+			reg = <0x13000000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_HSI1_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_HSI1_MMC_CARD>,
+				 <&cmu_top CLK_DOUT_CMU_HSI1_PCIE>,
+				 <&cmu_top CLK_DOUT_CMU_HSI1_UFS_CARD>,
+				 <&cmu_top CLK_DOUT_CMU_HSI1_UFS_EMBD>;
+			clock-names = "oscclk",
+				      "bus",
+				      "mmc_card",
+				      "pcie",
+				      "ufs_card",
+				      "ufs_embd";
+		};
+
 		pinctrl_hsi1: pinctrl@13040000 {
 			compatible = "samsung,exynos990-pinctrl";
 			reg = <0x13040000 0x1000>;