new file mode 100644
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/samsung,s2mpg10-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S2MPG10 Power Management IC regulators
+
+maintainers:
+ - André Draszik <andre.draszik@linaro.org>
+
+description: |
+ This is part of the device tree bindings for the S2MG10 Power Management IC
+ (PMIC).
+
+ The S2MPG10 PMIC provides 10 buck and 31 LDO regulators.
+
+ See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
+ additional information and example.
+
+definitions:
+ s2mpg10-ext-control:
+ properties:
+ samsung,ext-control:
+ description: |
+ These rails can be controlled via one of several possible external
+ (hardware) signals. If so, this property configures the signal the PMIC
+ should monitor. For S2MPG10 rails where external control is possible other
+ than ldo20m, the following values generally corresponding to the
+ respective on-chip pin are valid:
+ - 0 # S2MPG10_PCTRLSEL_ON - always on
+ - 1 # S2MPG10_PCTRLSEL_PWREN - PWREN pin
+ - 2 # S2MPG10_PCTRLSEL_PWREN_TRG - PWREN_TRG bit in MIMICKING_CTRL
+ - 3 # S2MPG10_PCTRLSEL_PWREN_MIF - PWREN_MIF pin
+ - 4 # S2MPG10_PCTRLSEL_PWREN_MIF_TRG - PWREN_MIF_TRG bit in MIMICKING_CTRL
+ - 5 # S2MPG10_PCTRLSEL_AP_ACTIVE_N - ~AP_ACTIVE_N pin
+ - 6 # S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG - ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL
+ - 7 # S2MPG10_PCTRLSEL_CPUCL1_EN - CPUCL1_EN pin
+ - 8 # S2MPG10_PCTRLSEL_CPUCL1_EN2 - CPUCL1_EN & PWREN pins
+ - 9 # S2MPG10_PCTRLSEL_CPUCL2_EN - CPUCL2_EN pin
+ - 10 # S2MPG10_PCTRLSEL_CPUCL2_EN2 - CPUCL2_E2 & PWREN pins
+ - 11 # S2MPG10_PCTRLSEL_TPU_EN - TPU_EN pin
+ - 12 # S2MPG10_PCTRLSEL_TPU_EN2 - TPU_EN & ~AP_ACTIVE_N pins
+ - 13 # S2MPG10_PCTRLSEL_TCXO_ON - TCXO_ON pin
+ - 14 # S2MPG10_PCTRLSEL_TCXO_ON2 - TCXO_ON & ~AP_ACTIVE_N pins
+
+ For S2MPG10 ldo20m, the following values are valid
+ - 0 # S2MPG10_PCTRLSEL_LDO20M_ON - always on
+ - 1 # S2MPG10_PCTRLSEL_LDO20M_EN_SFR - VLDO20M_EN & LDO20M_SFR
+ - 2 # S2MPG10_PCTRLSEL_LDO20M_EN - VLDO20M_EN pin
+ - 3 # S2MPG10_PCTRLSEL_LDO20M_SFR - LDO20M_SFR in LDO_CTRL1 register
+ - 4 # S2MPG10_PCTRLSEL_LDO20M_OFF - disable
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 14
+
+ samsung,ext-control-gpios:
+ description: |
+ For rails where external control is done via a GPIO, this optional
+ property describes the GPIO line used.
+
+ maxItems: 1
+
+ dependentRequired:
+ samsung,ext-control-gpios: [ "samsung,ext-control" ]
+
+patternProperties:
+ # 10 bucks
+ "^buck([1-9]|10)m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single buck regulator.
+
+ properties:
+ regulator-ramp-delay:
+ enum: [6250, 12500, 25000]
+ default: 6250
+
+ allOf:
+ - $ref: "#/definitions/s2mpg10-ext-control"
+
+ # 13 standard LDOs
+ "^ldo([12]|2[1-9]|3[0-1])m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for single LDO regulator.
+
+ properties:
+ regulator-ramp-delay: false
+
+ # 14 LDOs with possible external control
+ "^ldo([3-9]|1[046-9]|20)m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ properties:
+ regulator-ramp-delay: false
+
+ allOf:
+ - $ref: "#/definitions/s2mpg10-ext-control"
+
+ # 4 LDOs with ramp support and possible external control
+ "^ldo1[1235]m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ properties:
+ regulator-ramp-delay:
+ enum: [6250, 12500]
+ default: 6250
+
+ allOf:
+ - $ref: "#/definitions/s2mpg10-ext-control"
+
+additionalProperties: false
+
+allOf:
+ - if:
+ anyOf:
+ - required: [buck8m]
+ - required: [buck9m]
+ then:
+ patternProperties:
+ "^buck[8-9]m$":
+ properties:
+ samsung,ext-control: false
+
+ - if:
+ required:
+ - ldo20m
+ then:
+ properties:
+ ldo20m:
+ properties:
+ samsung,ext-control:
+ maximum: 4
@@ -22006,6 +22006,7 @@ F: drivers/mfd/sec*.[ch]
F: drivers/regulator/s2m*.c
F: drivers/regulator/s5m*.c
F: drivers/rtc/rtc-s5m.c
+F: include/dt-bindings/regulator/samsung,s2m*.h
F: include/linux/mfd/samsung/
SAMSUNG S3C24XX/S3C64XX SOC SERIES CAMIF DRIVER
new file mode 100644
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2021 Google LLC
+ * Copyright 2025 Linaro Ltd.
+ *
+ * Device Tree binding constants for the Samsung S2MPG1x PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
+#define _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
+
+/*
+ * Several regulators may be controlled via external signals instead of via
+ * software. These constants describe the possible signals for such regulators
+ * and generally correspond to the respecitve on-chip pins. The constants
+ * suffixed with _TRG enable control using the respective bits in the
+ * MIMICKING_CTRL register instead.
+ *
+ * S2MPG10 regulators supporting these are:
+ * - buck1m .. buck7m buck10m
+ * - ldo3m .. ldo19m
+ *
+ * ldo20m supports external control, but using a different set of control
+ * signals.
+ */
+#define S2MPG10_PCTRLSEL_ON 0x0 /* always on */
+#define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */
+#define S2MPG10_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */
+#define S2MPG10_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */
+#define S2MPG10_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */
+#define S2MPG10_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */
+#define S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */
+#define S2MPG10_PCTRLSEL_CPUCL1_EN 0x7 /* CPUCL1_EN pin */
+#define S2MPG10_PCTRLSEL_CPUCL1_EN2 0x8 /* CPUCL1_EN & PWREN pins */
+#define S2MPG10_PCTRLSEL_CPUCL2_EN 0x9 /* CPUCL2_EN pin */
+#define S2MPG10_PCTRLSEL_CPUCL2_EN2 0xa /* CPUCL2_E2 & PWREN pins */
+#define S2MPG10_PCTRLSEL_TPU_EN 0xb /* TPU_EN pin */
+#define S2MPG10_PCTRLSEL_TPU_EN2 0xc /* TPU_EN & ~AP_ACTIVE_N pins */
+#define S2MPG10_PCTRLSEL_TCXO_ON 0xd /* TCXO_ON pin */
+#define S2MPG10_PCTRLSEL_TCXO_ON2 0xe /* TCXO_ON & ~AP_ACTIVE_N pins */
+
+#define S2MPG10_PCTRLSEL_LDO20M_ON 0x0 /* always on */
+#define S2MPG10_PCTRLSEL_LDO20M_EN_SFR 0x1 /* LDO20M_EN & LDO20M_SFR */
+#define S2MPG10_PCTRLSEL_LDO20M_EN 0x2 /* VLDO20M_EN pin */
+#define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTRL1 register */
+#define S2MPG10_PCTRLSEL_LDO20M_OFF 0x4 /* disable */
+
+#endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */
The S2MPG10 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, RTC, clock outputs, and additional GPIOs interfaces. It has 10 buck and 31 LDO rails. Several of these can either be controlled via software or via external signals, e.g. input pins connected to a main processor's GPIO pins. Add documentation related to the regulator (buck & ldo) parts like devicetree definitions, regulator naming patterns, and additional properties. S2MPG10 is typically used as the main-PMIC together with an S2MPG11 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the rails with an 'm'. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- .../regulator/samsung,s2mpg10-regulator.yaml | 147 +++++++++++++++++++++ MAINTAINERS | 1 + .../regulator/samsung,s2mpg10-regulator.h | 48 +++++++ 3 files changed, 196 insertions(+)