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[Linaro-uefi,Linaro-uefi,v3,1/3] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue.

Message ID 1491827595-84884-2-git-send-email-chenhui.sun@linaro.org
State New
Headers show
Series D03/D05 platforms bug fix | expand

Commit Message

Chenhui Sun April 10, 2017, 12:33 p.m. UTC 
The I350 Hilink state is not stable, so we need to modify the
rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: shaochangliang <shaochangliang@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Signed-off-by: Chenhui Sun <chenhui.sun@linaro.org>
---
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++
 2 files changed, 6 insertions(+)
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Patch

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index 0b5a659..a9b3d74 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -470,6 +470,8 @@  VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
             RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
             Value |= (1 << 20); //bit 20: rxvalid enable
             RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+            RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \
+              CH_RXTX_STATUS_CFG_EN | CH_RXTX_STATUS_CFG);
         }
         PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
         RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
index 9671c57..9a0f636 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -70,6 +70,10 @@ 
 
 #define PCS_SDS_CFG_REG            0x204
 #define SDS_CFG_STRIDE             0x4
+#define MUX_LOS_ALOS_REG_OFFSET    0x508
+#define MUX_CFG_STRIDE             0x4
+#define CH_RXTX_STATUS_CFG_EN      BIT1
+#define CH_RXTX_STATUS_CFG         BIT2
 #define RegWrite(addr,data)            MmioWrite32((addr), (data))
 #define RegRead(addr,data)             ((data) = MmioRead32 (addr))