From patchwork Fri May 6 14:32:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67284 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp352878qge; Fri, 6 May 2016 07:34:42 -0700 (PDT) X-Received: by 10.50.180.202 with SMTP id dq10mr11080393igc.37.1462545282075; Fri, 06 May 2016 07:34:42 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id e10si10885906igo.62.2016.05.06.07.34.41; Fri, 06 May 2016 07:34:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 844FD6161C; Fri, 6 May 2016 14:34:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id C8EFD61607; Fri, 6 May 2016 14:33:34 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3333A61605; Fri, 6 May 2016 14:33:16 +0000 (UTC) Received: from mail-wm0-f53.google.com (mail-wm0-f53.google.com [74.125.82.53]) by lists.linaro.org (Postfix) with ESMTPS id 5C582615CD for ; Fri, 6 May 2016 14:33:14 +0000 (UTC) Received: by mail-wm0-f53.google.com with SMTP id n129so60446519wmn.1 for ; Fri, 06 May 2016 07:33:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YjuMj8RgAFuCVS9JQvL7cf66+oo+ETX8n9L7ZtcmpoE=; b=bQC1njxWdIqhhNrnUTLpUAZvzC2CzNhxqq9IWnFnhIq1ZM5WXWyCXWm5OtLfv0mZwj smjXM7L7yyKMq+pJbDLwTyV+liVfp57xP/1N+senFXrRsOrVWlQEOS+iGCBQCXcIojoI ltF9qxeIMWZbUWRKBz+o2lAYlr1li6XhnID87DOTNEH80M3Swx9VNvz6G2Kl2teos+9z S6n9V7xgTqPCVM8IXyUE8dAgXxAOZSdLAHzSt7ChTo76uOKiKSNKkbNuJdJxP69wUwVM M7Q485GlOOLGOkeLQC6ngufbs1m71twZr0Q+0eJbnAyaz0w0XutWN1Z8zPUOCHyBRvFw ML9g== X-Gm-Message-State: AOPr4FXShLm815ieyFOYCIf1YZ6ncfEC4SlMI8JHbnU8iIWjwJ+ezRf49B1l5B529Il0y75VCIw= X-Received: by 10.194.14.6 with SMTP id l6mr23210510wjc.48.1462545193525; Fri, 06 May 2016 07:33:13 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id on2sm15293942wjc.32.2016.05.06.07.33.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 May 2016 07:33:12 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@Lists.linaro.org, leif.lindholm@linaro.org Date: Fri, 6 May 2016 16:32:59 +0200 Message-Id: <1462545180-7941-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1462545180-7941-1-git-send-email-ard.biesheuvel@linaro.org> References: <1462545180-7941-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 3/4] Platforms/AMD/Styx: reallocate the in-memory copy of the varstore FV X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Before the DXE core has a chance to overwrite the in-memory copy of the varstore FV, relocate it to a dynamically allocated buffer. Note that, while this allocation is not made from the temporary PEI heap, the bookkeeping involved in calling AllocateAlignedRuntimePages() appears to push the envelope slightly, and so we need to increase the initial stack size (which is actually stack + heap) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 5 ++- Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c | 41 ++++++++++++++++++++ Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 9 +++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 6 ++- 4 files changed, 59 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 892068f62025..458b444159fc 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -401,7 +401,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # Stacks for MPCores in Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x6000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 # Stacks for MPCores in Monitor Mode @@ -537,6 +537,9 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5 !endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 ################################################################################ # diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index 971e3a193d91..4f7f6bb1c942 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -56,6 +57,44 @@ InitMmu ( } } +STATIC +VOID +MoveNvStoreImage ( + VOID + ) +{ + VOID *OldBase, *NewBase; + UINTN Size; + + // + // Move the in-memory image of the NV store firmware volume to a dynamically + // allocated buffer. This gets rid of the annoying static memory reservation + // at the base of memory where all other UEFI allocations are near the top. + // + OldBase = (VOID *)FixedPcdGet64 (PcdFlashNvStorageOriginalBase); + + Size = FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize); + + NewBase = AllocateAlignedRuntimePages (EFI_SIZE_TO_PAGES (Size), SIZE_64KB); + ASSERT (NewBase != NULL); + + CopyMem (NewBase, OldBase, Size); + + DEBUG ((EFI_D_INFO, "%a: Relocating NV store FV from %p to %p\n", + __FUNCTION__, OldBase, NewBase)); + + PcdSet64 (PcdFlashNvStorageVariableBase64, (UINT64)NewBase); + + PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, (UINT64)NewBase + + FixedPcdGet32 (PcdFlashNvStorageVariableSize)); + + PcdSet64 (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase + + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)); +} + /*++ Routine Description: @@ -135,5 +174,7 @@ MemoryPeim ( BuildMemoryTypeInformationHob (); } + MoveNvStoreImage (); + return EFI_SUCCESS; } diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index c1cca09da3ff..8b35d9f604be 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -80,9 +80,18 @@ gAmdStyxTokenSpaceGuid.PcdNsISCPMemoryBase gAmdStyxTokenSpaceGuid.PcdNsISCPMemorySize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase + [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + [Depex] gAmdStyxPlatInitPpiGuid diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 32d97c017b46..60d1c8ecbbaf 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -404,7 +404,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # Stacks for MPCores in Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x6000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 # Stacks for MPCores in Monitor Mode @@ -549,6 +549,10 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5 !endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 + ################################################################################ #