From patchwork Tue May 10 12:11:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67437 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp2090894qge; Tue, 10 May 2016 05:12:29 -0700 (PDT) X-Received: by 10.55.22.169 with SMTP id 41mr20043190qkw.111.1462882349262; Tue, 10 May 2016 05:12:29 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j60si1196692qge.40.2016.05.10.05.12.29; Tue, 10 May 2016 05:12:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id DD7EA6166C; Tue, 10 May 2016 12:12:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id EFAA26163E; Tue, 10 May 2016 12:12:08 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 363076163B; Tue, 10 May 2016 12:12:04 +0000 (UTC) Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by lists.linaro.org (Postfix) with ESMTPS id DA57561585 for ; Tue, 10 May 2016 12:12:01 +0000 (UTC) Received: by mail-wm0-f52.google.com with SMTP id a17so24018612wme.0 for ; Tue, 10 May 2016 05:12:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=78ncmrfgIRen3OMx1d38D0EfCvMwYnMrO52VL9IB8hs=; b=Sc/94lwhVaiYY8QVJQZepMTQ/Nio6pjhDlLJWjhR1UVlqdgL8ydkyxosyHmWT8Yrhb okjZBuH7IaTANYuWhV6p/Az3VK0q/R9WFyjNrVtSaTISTu+u0JaI0G+aTZh0ab3WvpVU EBcMIC5ID/JpuT3b6XFr1nbtKw1J+AH5IgWkTKHXk6qJEe5wdaxjZQEjUdb/2AroOzGf w+0uavvih4Mmewsc9gluHgCJsqV8qNPiyQ/GMTirF39IGP6WMqPoaFv2sOmtzodH1aYp t05gmKOGMy/QhMKJPiGLRN0+sRgkJziRpXzF9HxbilqCd5xezNZNMvp+nzVlm3eSfVLM tMMQ== X-Gm-Message-State: AOPr4FUgYQ68PeK78u+g+5ouy+nysFLOFxQ4AcAMTb3OHpKhrlpIRLVvW6DbNJQM0RBSZFdI+qw= X-Received: by 10.194.153.65 with SMTP id ve1mr34104349wjb.106.1462882321067; Tue, 10 May 2016 05:12:01 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id m20sm2623084wma.23.2016.05.10.05.11.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 May 2016 05:12:00 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Tue, 10 May 2016 14:11:40 +0200 Message-Id: <1462882313-7637-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1462882313-7637-1-git-send-email-ard.biesheuvel@linaro.org> References: <1462882313-7637-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 01/14] Platforms/AMD/Styx/FdtDxe: retrieve spin-table addresses for private HOB X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Rather then accessing the ARM_PROCESSOR_TABLE configuration table, retrieve the mailbox addresses for secondaries from the private HOB. This allows us to deprecate and ultimately get rid of this configuration table, since it exposes platform internals via an OS visible table, and this should be avoided if possible. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c index 044ec8b33f9d..2768475aeda2 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c @@ -382,7 +382,6 @@ AmdStyxPrepareFdt ( CHAR8 Name[10]; LIST_ENTRY ResourceList; BDS_SYSTEM_MEMORY_RESOURCE *Resource; - ARM_PROCESSOR_TABLE *ArmProcessorTable; ARM_CORE_INFO *ArmCoreInfoTable; UINTN ArmCoreCount; UINT32 PrimaryClusterId; @@ -547,13 +546,8 @@ AmdStyxPrepareFdt ( // in the kernel documentation: // Documentation/devicetree/bindings/arm/cpus.txt // - ArmProcessorTable = AmdStyxGetArmProcessorTable(); - ASSERT_EFI_ERROR (ArmProcessorTable == NULL); - ArmCoreInfoTable = ArmProcessorTable->ArmCpus; - - // Make sure SoC's core count does not exceed what we want to build - ArmCoreCount = ArmProcessorTable->NumberOfEntries; - ASSERT_EFI_ERROR (ArmCoreCount > NUM_CORES); + ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&ArmCoreCount); + ASSERT (ArmCoreCount <= NUM_CORES); // Get Id from primary CPU MpId = (UINTN) ArmReadMpidr ();